This year’s EDSFair, held in late January, once again provided a trove of useful information on chip design and verification trends in Japan. For example, a large number of designers who stopped by the EVE booth said that the size of their SoC was more than 50-million gates. Another significantly sized group said that their designs reached 50-million gates, while an ample number noted that the size of their design was approximately 20-million gates. From there, smaller numbers of designers reported that their chip designs were in the 40 million-, 30 million- or five million-gate range.
In previous years, we had not asked attendees to share their thoughts about transaction-level modeling (TLM-2.0) or either power format. We did this year and learned that many designers are already adopting OSCI’s TLM-2.0 and Si2’s Common Power Format (CPF). Accellera’s Unified Power Format (UPF) is also gaining traction in Japan.
According to EDSFair attendees we met, ARM cores are the predominant processors used in their SoC designs by a whopping 70 percent and leaving all others in the dust. We compared statistics from last year’s survey to this year’s and found that 10 percent of ARM users have moved to the Cortex technology from legacy ARM processor technology.
DDR2 SDRAM and DDR3 SDRAM seem to be the prevailing embedded memory cores, according to those we polled. Again, comparing statistics from year to year shows that there has been no appreciable technical movement.
In another nod to ARM, the AMBA3 AHB and AMBA3 AXI bus interfaces were mentioned most often in our discussions.
Additionally, forty-five percent said that Xilinx FPGAs are the ones they use for prototyping, with 38 percent listed Altera FPGAs.
We spoke with a good number of the EDSFair attendees over those two days. Designers made up 50 percent of our visitors, with 24 percent listing their occupation as EDA tool support specialists. Thirteen percent were verification engineers, another two percent system architects. Eleven percent listed other. Seventy-six percent came from the engineering ranks, with 24 percent from management.
Once again, Verilog is the language most commonly used for ASIC design (51 percent), with VHDL coming in at 17 percent. SystemC clocked in at 13 percent and SystemVerilog was a seven percent. For testbench design, Verilog dominates again at 47 percent, with SystemVerilog at 18 percent. SystemC came in at 12 percent, with VHDL closely behind at 11 percent.
The majority of our visitors (88 percent) told us that they had less than 100 simulation seats, while five percent said they had between 100-200 and seven percent had more than 200 seats. Which simulator is the most popular in Japan? Well, think of the three most popular simulators on the market today. All three match up well –– only an 11 percentage point spread between the three –– in our mini-survey.
Overall, EVE visitors noted that they are reasonably satisfied with their current verification flow. This was based on runtime performance, setup time, efficiency in catching corner cases and reusability. All appear to be evaluating hardware-assisted verification platforms over the next six to 12 months. Ranking the importance of their buying criteria, most said simulation acceleration and transaction-based emulation are high on their wish lists. In-circuit emulation and visibility into the design came next, followed by compilation performance and runtime. While price did not score highly with survey respondents, we know price is important. Presumably, this is because they are designers evaluating tools on their technical merits. Their managers, however, consider price as one of the most important criteria.
Those using hardware-assisted verification report that their primary application is ASIC validation, with hardware/software co-verification a close second. A good number of those polled (48 percent) said that they use these tools for simulation acceleration, with transactor-based emulation a distant second at 43 percent. Another 11 percent listed in-circuit emulation, while eight percent listed standalone emulation as the mode they use.
The information we gleaned from this year’s EDSFair is invaluable and we’re grateful to the many attendees who stopped by the EVE booth to talk. We’ll compare their comments and feedback with those we collect from other conferences throughout 2011 and use it for planning purposes.
About the author:
is general manager of EVE-USA
(San Jose, Calif.). He has more than 30 years of experience in EDA and ATE, where he held responsibilities in top management, product marketing, technical marketing and engineering.