Good timing: Memory IP

It seems that one of the greatest opportunities for innovation in memory is the controller. For instance, a lot of work is being done to improve and customize the controllers for different applications of solid state drives (SSDs). And, today, Uniquify, a startup in Silicon Valley, announced that it has been granted a US patent on "Critical DDR2/DDR3 Timing Innovation for Chip Designs."

This company is by no means a "new kid on the block," because its DDR1, DDR2, DDR3 and DDR2/3 IP products have already been licensed to companies worldwide. Uniquify uses its self-calibrating logic IP in the physical layer of its memory controller IP. Now, the company has been granted a United States patent covering its DDR (double data rate) memory controllers in regard to timing requirements, allowing memory controllers to automatically fine-tune critical timing parameters after the SoCs are installed in system boards.

Here's how it works. Uniquify memory controller IP performs a system self-test on power-up that allows the controller’s PHY circuitry to automatically fine-tune timing parameters every time the host SoC is reset. The company expects this to also improve  yield due to the ability to automatically adapt timing characteristics for a wide range of system-level design choices and for variations in the SoC foundry process.

What do you think? Does this sound like a better approach than what you've done in the past? Sound off below.