Commentary
Survey points to variation-aware design as top custom IC focus
Amit Gupta
4/29/2011 9:51 AM EDT
Two-thirds of designers and managers named variation-aware design as a top segment where technology advancement is needed over 2011 and 2012. This was a key finding of a blind global survey of 486 engineers and engineering managers on Variation-Aware Custom IC Design.
As shown in Figure 1, the second tier of technologies identified were parasitic extraction (48 percent), simulation (44 percent) and physical verification (40 percent). The third tier technologies were layout (26 percent) and routing (24 percent). Schematic capture was identified by only 7 percent of respondents.
To help understand why tools for managing variation ranked so high, let’s take a look at what survey respondents cited as their main reasons to do variation-aware custom IC design.
- Improve parametric yield (74 percent). The move to smaller process nodes is driven by the need for better product performance, lower power consumption and reduced area. However, smaller geometries also create increased design variation issues such as random effects, environmental conditions, and layout-dependent effects. Variation impacts silicon performance and yield versus the predicted performance and yield in simulation.
Without variation-aware design, designers have no choice but to deal with variation by over-margining or under-designing. Both methods are costly; they either vastly underutilize the benefits of node migration or waste money on failed silicon. The impact of variation is further compounded when you consider that most semiconductor companies use the same handful of foundries for silicon manufacture. To differentiate themselves competitively, companies need to get the most out of each transistor.
- Avoid respins. (64 percent), Avoid project delays (25 percent). When we combine these two areas, we find that 89 percent saw variation-aware design as vital to avoiding time-to-market delays. In fact, a related survey finding uncovered that 53 percent of engineers and managers indicated their organizations had actually missed a project deadline, delayed a tapeout, or required a respin due to variation problems. For those that experienced delays, the average time lost was a remarkable 2 work months.
- Save designer time (20 percent). The designers spent an average of 22 percent of their time managing design variation.
It is essential to provide context as to which nodes companies cite as critical points to begin incorporating variation-aware design practices. As shown in figure 2 below, 37 percent of designers and managers identified variation-aware design as important at 90 nanometers and 60 percent at 65 nanometers. A whopping 85 percent declared variation-aware design to be important at 45 nanometers.
Figure 2
As shown in Figure 1, the second tier of technologies identified were parasitic extraction (48 percent), simulation (44 percent) and physical verification (40 percent). The third tier technologies were layout (26 percent) and routing (24 percent). Schematic capture was identified by only 7 percent of respondents.
Figure 1
To help understand why tools for managing variation ranked so high, let’s take a look at what survey respondents cited as their main reasons to do variation-aware custom IC design.
- Improve parametric yield (74 percent). The move to smaller process nodes is driven by the need for better product performance, lower power consumption and reduced area. However, smaller geometries also create increased design variation issues such as random effects, environmental conditions, and layout-dependent effects. Variation impacts silicon performance and yield versus the predicted performance and yield in simulation.
Without variation-aware design, designers have no choice but to deal with variation by over-margining or under-designing. Both methods are costly; they either vastly underutilize the benefits of node migration or waste money on failed silicon. The impact of variation is further compounded when you consider that most semiconductor companies use the same handful of foundries for silicon manufacture. To differentiate themselves competitively, companies need to get the most out of each transistor.
- Avoid respins. (64 percent), Avoid project delays (25 percent). When we combine these two areas, we find that 89 percent saw variation-aware design as vital to avoiding time-to-market delays. In fact, a related survey finding uncovered that 53 percent of engineers and managers indicated their organizations had actually missed a project deadline, delayed a tapeout, or required a respin due to variation problems. For those that experienced delays, the average time lost was a remarkable 2 work months.
- Save designer time (20 percent). The designers spent an average of 22 percent of their time managing design variation.
It is essential to provide context as to which nodes companies cite as critical points to begin incorporating variation-aware design practices. As shown in figure 2 below, 37 percent of designers and managers identified variation-aware design as important at 90 nanometers and 60 percent at 65 nanometers. A whopping 85 percent declared variation-aware design to be important at 45 nanometers.
Figure 2
What is the bottom line - what are these semiconductor organizations’ direct plans for variation-aware design? The survey showed that 23 percent of design organizations already have variation-aware design tools deployed. Another 24 percent intend to implement them in 2011. This data points to a remarkable 100 percent growth in organizational adoption of such tools over the coming year.
To assist design organizations in effectively managing variation, commercial tools must sufficiently reduce the time required to analyze the impact of variation on meeting design specifications, so that designers can readily incorporate such analysis as part of their standard design process. When the design specification fails due to variation, commercial tools are needed to automatically identify and present ‘variation bugs’, or variation-sensitive devices, to the designer.
Commercial tools should propose remedies to fix the variation bugs identified, while allowing designers to retain direct control over implementing any design changes. It should be straightforward for designers to deploy the fix and re-verify that the design is robust for variation. Finally, any new variation-aware design tools must be integrated seamlessly into existing custom IC design flows including design environments, True SPICE and Fast SPICE simulators.
For information on Solido Variation Designer, click here.
About the author:
Amit Gupta, President & CEO, Solido Design Automation Inc.
To assist design organizations in effectively managing variation, commercial tools must sufficiently reduce the time required to analyze the impact of variation on meeting design specifications, so that designers can readily incorporate such analysis as part of their standard design process. When the design specification fails due to variation, commercial tools are needed to automatically identify and present ‘variation bugs’, or variation-sensitive devices, to the designer.
Commercial tools should propose remedies to fix the variation bugs identified, while allowing designers to retain direct control over implementing any design changes. It should be straightforward for designers to deploy the fix and re-verify that the design is robust for variation. Finally, any new variation-aware design tools must be integrated seamlessly into existing custom IC design flows including design environments, True SPICE and Fast SPICE simulators.
For information on Solido Variation Designer, click here.
About the author:
Amit Gupta, President & CEO, Solido Design Automation Inc.Amit Gupta is co-founder, President & CEO of Solido Design Automation Inc. In 1999, he co-founded Analog Design Automation Inc. (ADA). Over the next five years, as President & CEO and VP Marketing and Business Development, Gupta helped the company grow through acquisition by Synopsys Inc. Prior to this, Gupta was product manager for the wireless group at Nortel Networks and a hardware engineer for the RF Communications group at Harris Corporation. He graduated with degrees in both Electrical Engineering and Computer Science with great Distinction from the University of Saskatchewan. He was awarded the 2005 outstanding alumni award for significant accomplishments since graduation.
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