SoC realization fills a void
This void, where important system level information must be transformed to the next level of abstraction and analyzed, is where I see the best growth opportunity for EDA. It is here where an SoC has more degrees of optimization and critical decisions are made on issues such as which building blocks are used, what operating characteristics the SoC will have, and whether it will work as intended once committed to a silicon device. It is the cockpit for guiding the design from concept to implementation and ensuring design coherence from one level to the next. It is also the place where software development finds its voice to impact hardware design.
To better understand this relationship let’s look at a high level SoC development flow. In early 2010, Cadence Design Systems presented a White Paper entitled “EDA360, the Way Forward for Electronic Design
”. That paper proposed a definition of the macro steps involved in electronic system design that, in my view, hit the mark. I will borrow some concepts and terminology from that piece here:
The development of a complete hardware/software platform that will provide all the necessary support for end-user applications. The platform includes one or more SoCs and adds an embedded software infrastructure that typically includes an OS, middleware, and reference applications. This step is increasingly driven by the system software applications that will run on the completed system.
: The new and critical “bridge” step to take a system concept to a well-defined design that can be implemented at a detailed level. It involves the all important steps of choosing the right architecture and IP, validation of the IP, assembling it all on a workable platform, and performing a variety of analysis and verification tasks to ensure that it can be implemented as a viable, working SoC device.
This represents the set of steps necessary to take a verified SoC design consisting of hardware and software functions, and implement it in working silicon. This is the domain of traditional EDA providers who work closely with semiconductor manufacturers such as TSMC. We often call this “EDA classic”.
Of the three steps, SoC Realization holds the most potential to dramatically improve SoC development time and bring new levels of value to the electronic design process. It is also the most adjacent area to EDA classic to consider and is today serviced by a fractured collection of in-house and commercial offerings. In a way, EDA needs to occupy all three domains. It is my belief that the path to System Realization requires a strong foundation of SoC Realization that is served piecemeal today. Figure 2
illustrates a macro view of a unified SoC development flow.
Figure 2: Unified SoC development flow