Viewpoint: How will the chip wars be won? -- Part 1

Ecosystem leadership
Intel’s focus on transistor performance can be traced back to the height of the PC wars when the benchmark was clock speed. While Intel focused on transistor performance, the foundries adapted Intel’s transistor innovations for their own SoC integration needs. In addition, they aggressively pursued metal density scaling and cost reduction. While Intel pursued a limited vertical functional integration, the foundries developed a lateral ecosystem and designed transistors for a variety of vendors that independently optimized functionality for each IP block (CPU, GPU, radio, modem, GPS, etc.).

This vast ecosystem of existing design IP is now a significant influencer on the adoption of the next transistor architecture. Arguably, the foundries are today better positioned for the SoC era in spite of having a non-leading edge transistor. TSMC has stated that in 2012 it will integrate a variety of IP blocks and ship highly complex mobile SoC parts to its customers. These processors will be made in 28nm technology and will likely set new benchmarks for cost, power and connectivity features. As an example, the Snapdragon processor by Qualcomm might well become the most highly integrated SoC to debut Windows 8 in 2012. Intel has the clear advantage at the transistor level and will win the CPU space, but the ecosystem has the advantage at the system level and is poised to win the SoC space.

“Making it smaller doesn’t help anymore”
Geometric scaling of the transistor below a pitch of 80nm tests the limits of traditional lithography. Innovations like double/triple patterning and spacer layer transfer are needed to print features below that pitch. Extreme ultra-violet (EUV) patterning has been in development for close to a decade as the
successor to 193i patterning but remains costly with limited throughput and ROI.

Since the foundries are ahead of Intel in metal pitch scaling, they will be the first to hit the immersion lithography limit and be required to transition to novel patterning techniques or ultimately EUV patterning. Even then, the cumulative cost of patterning will be so high that cost-per-gate is expected to stay flat or even go up when scaling to the 20nm node. It is unlikely that foundries will be able to execute two radical changes (tri-gate and new patterning) within the traditional 2 year development cycle. The 28/20nm nodes will be very long lived as foundries grapple with increased cost and complexity in addition to traditional scaling challenges. This will be another inflection point in the morphing of the traditional Moore’s Law metric of cost-per-gate.  

“Cost-per-goodness” replaces “cost-per-gate”
In the SoC era, as “cost-per-gate” plateaus, the new driver will be “cost-per-goodness”. Packing as many features (goodness) on a chip as possible at the lowest integrated system cost and power will win. However the cost to design that functionality is also increasing rapidly.

New 28nm chip designs cost as high as $200M compared to 45nm designs which cost <$100M. While the bulk of this increase is attributed to design complexity, mask costs and embedded software costs are also increasing significantly.

The transistor architecture that is most compatible with all the IP needs of a complex SoC at the lowest cost will thus have the upper hand. As technology development lifecycles get longer and product lifecycles get shorter, foundries will try to extract all the goodness in an existing transistor technology before moving to the next one.


[Part two of this article will discuss potential paradigm shifts in the SoC era. As scaling hits physical and economic limits, the industry will continue to innovate more than ever before, but that innovation will likely be centered on extending the life of an existing geometry, rather than be driven by scaling
the geometry itself.]


-- Pushkar Ranade is director of process integration at SuVolta, Inc. Prior to joining SuVolta in 2010, Ranade was with Intel Corporation where he contributed to transistor process integration and development of Intel’s 65nm, 45nm and 22nm logic technology. Ranade joined Intel in 2003 after graduating with a Ph.D. from the University of California, Berkeley. At Berkeley, his research was in the area of sub-70nm CMOS transistor design and involved the integration of novel gate materials and ultra-shallow junctions. The opinions expressed here are his alone,and do not reflect those of EE Times.