Commentary
The fabless-foundry model will survive (at least through 14-nm)
Handel Jones
6/15/2012 6:59 PM EDT
Editor's note: This article was rewritten in rebutal to comments made in April by Mark Bohr, an Intel Senior Fellow. As reported by EE Times, Bohr said the fabless-foundry model is"collapsing."
What are the problems?
1. Parametric yields at 28 nm are not at expected levels. Process variables such as random dopant fluctuations, line width and line gap variations, and via resistance, which affect RC-related timing issues, result in both unpredictable and low parametric yields for the targeted specifications. The process variables have increasing impact on leakage, power consumption and yields.
A perspective on the challenges facing foundry vendors and fabless companies is shown in the following figure.
Click on image to enlarge.
To address the chasm problem areas, an IDM-type interface is required between process teams at the foundry vendors and design teams at the fabless companies.
Large fabless companies and foundry vendors have the financial resources to set up the required interfaces and collaborate on resolving problems. Smaller companies will face financial challenges.
A key issue is who establishes and pays for these IDM-type disciplines? Fabless company, foundry, or both? It is likely that many of the costs and disciplines will need to be shared.
2. Increasing capex requirements for being a leader in the foundry business. TSMC’s CAPEX in 2012 is $8 billion, which at $1 billion per 10,000 wafers, gives additional capacity of 80,000 wafers per month at 28 nm and 20 nm. Samsung’s nonmemory capex is also likely to be $8 billion in 2012 ($6.5 billion announced), which will give an additional 80,000 wafers per month as well. Globalfoundries is ramping output from its Malta fab and building capacity to 30,000 wafers per month in 2012 in addition to the 80,000 wafers per month already in Dresden. UMC’s capex in 2012 is $2 billion, but the company has announced that Fab 12 will receive $8 billion in funding. UMC will likely need a funding partner in order to invest the $8 billion in the near term.
Only a small number of companies will be able to invest the required capex for large wafer capacity through the 14-nm technology node. Fabless companies will, however, need to select which foundry vendor partner they collaborate with.
3. Higher process complexity as feature dimensions shrink. A major problem for IDMs as well as foundry vendors is that the cost of developing advanced processes increases as feature dimensions shrink, a perspective of which is shown below.
Click on image to enlarge.
The cost for 20 nm is based on bulk CMOS, and 14 nm is based on FinFET (it is understood that Intel is using FinFET at 22-nm). The cost of developing the FinFET process is between $2 billion and $3 billion for the leaders and will be $1.8 billion for close followers. With R&D at 10 percent of revenues, revenues will need to be $9 billion, with process technology development over two years. Having the appropriate wafer processing and wafer fab facilities at 14 nm will cost more than $5 billion for 40,000 wafers per month.
The migration to 450-mm will require an investment of $10 billion for 40K wafers per month, with revenue potential of $10 billion per year. The only participants will be those with access to large financial resources, but payback can be good for foundry vendors that establish appropriate business models.
It is a high-risk, high-reward environment. If foundry/fabless companies establish an IDM-type interface, there is no reason that they cannot be as effective as an IDM.
Next: Payback
What are the problems?
1. Parametric yields at 28 nm are not at expected levels. Process variables such as random dopant fluctuations, line width and line gap variations, and via resistance, which affect RC-related timing issues, result in both unpredictable and low parametric yields for the targeted specifications. The process variables have increasing impact on leakage, power consumption and yields.
A perspective on the challenges facing foundry vendors and fabless companies is shown in the following figure.
Click on image to enlarge.
To address the chasm problem areas, an IDM-type interface is required between process teams at the foundry vendors and design teams at the fabless companies.
Large fabless companies and foundry vendors have the financial resources to set up the required interfaces and collaborate on resolving problems. Smaller companies will face financial challenges.
A key issue is who establishes and pays for these IDM-type disciplines? Fabless company, foundry, or both? It is likely that many of the costs and disciplines will need to be shared.
2. Increasing capex requirements for being a leader in the foundry business. TSMC’s CAPEX in 2012 is $8 billion, which at $1 billion per 10,000 wafers, gives additional capacity of 80,000 wafers per month at 28 nm and 20 nm. Samsung’s nonmemory capex is also likely to be $8 billion in 2012 ($6.5 billion announced), which will give an additional 80,000 wafers per month as well. Globalfoundries is ramping output from its Malta fab and building capacity to 30,000 wafers per month in 2012 in addition to the 80,000 wafers per month already in Dresden. UMC’s capex in 2012 is $2 billion, but the company has announced that Fab 12 will receive $8 billion in funding. UMC will likely need a funding partner in order to invest the $8 billion in the near term.
Only a small number of companies will be able to invest the required capex for large wafer capacity through the 14-nm technology node. Fabless companies will, however, need to select which foundry vendor partner they collaborate with.
3. Higher process complexity as feature dimensions shrink. A major problem for IDMs as well as foundry vendors is that the cost of developing advanced processes increases as feature dimensions shrink, a perspective of which is shown below.
Click on image to enlarge.
The cost for 20 nm is based on bulk CMOS, and 14 nm is based on FinFET (it is understood that Intel is using FinFET at 22-nm). The cost of developing the FinFET process is between $2 billion and $3 billion for the leaders and will be $1.8 billion for close followers. With R&D at 10 percent of revenues, revenues will need to be $9 billion, with process technology development over two years. Having the appropriate wafer processing and wafer fab facilities at 14 nm will cost more than $5 billion for 40,000 wafers per month.
The migration to 450-mm will require an investment of $10 billion for 40K wafers per month, with revenue potential of $10 billion per year. The only participants will be those with access to large financial resources, but payback can be good for foundry vendors that establish appropriate business models.
It is a high-risk, high-reward environment. If foundry/fabless companies establish an IDM-type interface, there is no reason that they cannot be as effective as an IDM.
Next: Payback
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the_floating_ gate
6/16/2012 12:03 AM EDT
If foundry/fabless companies establish an IDM-type interface, there is no reason that they cannot be as effective as an IDM.
Brilliant analysis
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the_floating_ gate
6/16/2012 12:07 AM EDT
It's all about to ramp a 450 mm fab - you need volume - lot's of volume - currently only Intel and NAND flash have the kind of volume to support a fast and economical ramp
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the_floating_ gate
6/16/2012 12:17 AM EDT
Satya Kumar – Credit Suisse
Yeah. Hi, thanks for taking my question, from Credit Suisse. Eric, you talked about the 14-nanometer multiple patterning having issues. Are you referring to 14-nanometer for Logic or were you referring to foundry processes?
Eric Meurice
Our foundry processes in the following sense that foundries are having another challenge that the IDMs would not have. The challenge is that they have to deliver design rules, which are less restrictive and they have to deliver shrink factor, which is very aggressive. So, yes, my comments on 14-nanometer being a competitor to being in the first to go concerns more the foundry environment than it concerns the microprocessor environment.
ASML
http://seekingalpha.com/article/507741-asml-holding-s-ceo-discusses-q1-2012-results-earnings-call-transcript?part=qanda
Listen and learn
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resistion
6/16/2012 2:30 PM EDT
The MP starts with loosened DRs to begin with.
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Or_Bach
6/16/2012 12:56 AM EDT
It seems that the partnership needs to include at least the EDA vendors and most likely the IP vendors as well. In the respect an IDM like Intel have a very significant advantage as achieving good partnership between to many stakeholders will be extremely hard to achieve. In fact Intel had already achieved few years of process lead and if anything this lead will keep on growing. We believe the best path for the foundries-fabless to win the game would be to change the court. An attractive path for such is clearly monolithic 3D. It seems the major foundries are moving toward that, by already investing heavily in 3D-IC (TSV base at this point).
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http://www.lulu.com/spotlight/poconoarmchairreview
6/16/2012 10:49 AM EDT
I believe I've seen this person somewhere before: http://www.eetimes.com/Content/uploads/327874.jpg
Hey, wait a minute: http://cdn.screenrant.com/wp-content/uploads/Lex-Luthor-Comic-Book.jpg
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resistion
6/16/2012 2:32 PM EDT
The key issue of 14 nm for foundry is cost and will there be enough customers.
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joshxdr
6/17/2012 9:53 AM EDT
Interesting article. The IDM-like relationship between design and process already exists for the biggest fabless companies, like Qualcomm, Nvidia, and AMD. Of course they can never have a seamless relationship like in a real IDM. Considering the very shaky state of the world economy, I think the projections for future fab business are much too rosy.
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sranje
6/18/2012 12:38 PM EDT
This is an outstanding article by a well informed and thoughtful professional. It actually confirms Intel Bohr's assertion of challenges ahead for fabless giants.
While Intel was fast to recognize the opportunity and increased the pace of nodal introduction - from two years to one year for 22nm and 14nm, Dr. Jones states that foundry nodal introductions will be slower than the historical two year pattern.
The nodal revenue distribution over time for foundries only is very informative. Is Samsung's Apple processors included or they are excluded and treated as Samsung ASICs? Note that by 2015 Apple processors units will be larger than Intel processor volume.
Interesting but somewhat predictable times ahead -- once one accepts that mobile application processors are just the same old - compute processors
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double-o-nothing
6/19/2012 9:04 AM EDT
ASML CEO couldn't candidly say at 10 nm even EUV would need double patterning (k1=0.24) and at 7 nm multiple patterning.
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resistion
6/26/2012 1:13 AM EDT
ARM Expects First 14nm Tape Outs in 2013
The head of ARM's processor division said Monday at Computex that ARM chips with 20-nanometer manufacturing process will appear in products in 2013, along with the first 14nm tape outs.
Simon Segarusu, Senior Vice President of ARM, said that said that the 28nm process is currently used in mass production and production tests of the first 20nm chips is expected to begin later this year, aiming at mass producing them by 2013. Multiple 20nm test chips are already taped out, including the dual-core Cortex-A15, ARM's executive said.
The first 14nm tape out is also expected to be tested at the same period, Segarusu added.
ARM's arcitecture is generally used by foundries (Samsung, UMC, TSMC, IBM, GLOBAlfoundries) and chip companies since it is offering low-power, high-performance chips that can be used in mobile, CE devices of even servers.
ARM hopes that it will gain a 20% of the server market by 2015.
Companies such as Qualcomm, Texas Instruments, Nvidia and Samsung have been licensing ARM's architecture.
http://www.cdrinfo.com/sections/news/Details.aspx?NewsId=33421
Are the foundries ready for 14 nm in 2013?
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