By Ajay Bhatt
Director, Architecture and Planning
Intel Digital Enterprise Group

As the lead architect on the Advanced Graphics Port (AGP) 4X and one of two chief architects on USB 1.0, I had a pretty good idea of the challenges the PCI Express team would face. Frankly, the biggest hurdle was convincing senior decision makers at Intel and other companies that developed PCI-and depended on it for successful products for a decade-that the interconnect had run its course, and we needed another universal interconnect with an equivalent life span for future applications. It quickly became apparent that the challenge boiled down to two issues: how much to change and how much to preserve.

These questions drove the greatest lessons I learned over the course of the project: the need to confer with many-and I mean many-people with different application backgrounds and needs, and then pull together tight, crisp requirements that remain stable over the duration of the program. The fact that we had to talk with so many people is evidence of the disruptive nature of PCI Express.

Naturally, those who had invested their resources into the stable PCI standard wanted to see the value from that investment preserved. At the same time, we had to meet the requirements for a new universal I/O interconnect for emerging applications across market segments as diverse as embedded, client, workstation, server and communications, among others.

In 2003, we started with a small group of promoters to develop the initial requirements and to champion PCI Express. Soon we included a diverse group of key developers. They helped further refine and solidify the requirements for a broad set of applications without undermining the program's long-term stability.

This disciplined approach stood in stark contrast to similar efforts that began with rough requirements and changed as the program developed. For PCI Express, that would have been a recipe for disaster.

The prerequisites for the program included an easy migration strategy from PCI to PCI Express, cross-platform applicability, features for specific market segments and rapid, easy deployment with high-volume technology.

Although PCI Express was new, our costs had to be in line with market realities. By defining a narrow, fast interconnect, we kept the system-level cost in the client to a four-layer motherboard with only two signal layers. Even though we knew we had to support Gigabit Ethernet and next-generation graphics, more layers precluded a price point at or below PCI costs.

PCI began as a 5-volt technology. We needed an interconnect that scaled with voltages and process technology, as well as width and frequency. We made sure PCI Express-based products could be comfortably built with the high-volume processes and packaging technology available in 2003.

When PCI was initiated, we thought 2-D graphics and 133-Mbyte/second I/O performance would be sufficient. With PCI Express, our starting point was high-performance applications, such as graphics, exceeding 4 Gbytes/s at introduction.

For the most part, the card-electromechanical spec pretty much used the chassis infrastructure we had in both clients and servers, which was a big savings and gave us a foundation we could use in the transition to new form factors. These new form factors let us upgrade systems without opening the box. We also had to be compatible with the PCI programming model so that systems could continue to utilize the software that exists today, including BIOSes and device drivers.

To address these uncertainties, we fostered from the beginning enabling seminars, design reviews and direct access for industry representatives to the people who wrote the spec. This led to one of the smoothest launches of a new, high-volume technology I have ever seen. Today, PCI Express supports multiple platform connection types-chip to-chip, board-to-board, docking station and new form factors.

I honestly believe we have created an evolutionary path for a technology that is having a revolutionary impact. It seems a bit trite to say fortune favors the prepared, but this has certainly proven to be the case with PCI Express. Because we were able to apply what we'd learned from our USB and AGP efforts, we were even more successful-success being defined as a technology entering the market with great acceptance and rapid deployment.