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By Zvi Or-Bach
Chairman, President and CTO
eASIC Corp.
It all started at a dinner event in the summer of 1982, while I worked for Honeywell Electro Optics Division as part of a special customization team. During that dinner I came up with a vision of a machine and accompanying design tools that would allow engineers to design a desired circuit and have the machine fabricate the custom prototype by a pushbutton operation.
One morning in early 1984, while I was shaving, the idea of using a laser for disconnecting IC links popped into my mind and, ultimately, drove me to invent a unique IC customization machine. We called it the QuICk System. This invention became the basis for founding Chip Express Corp.
Later I felt what many engineers feel after completing a project. "If only I could start it all over again ..."
In early 1999, just such an opportunity presented itself. I had just left Chip Express after bringing it to $40 million in revenue, 1,000 ASIC designs delivered, secured funding and strategic relations with Lucent.
It did not take long to reaffirm my disbelief in the conventional wisdom circa 1999 that the success of FPGAs and standard-cell ASICs must force gate array technology out of the market. In fact, I realized that the space in between FPGAs and standard cells increases with every new process node. But it was true that the conventional gate array was losing its value with every additional metal layer.
Looking forward, I observed that any new process node now comes with an additional two metal layers, and I came up with a new type of structured-ASIC technology. On March 11, 1999, I filed the first patent to protect the idea of blending an array of bit-stream programmable-logic cells on a substrate with a mask-defined interconnection fabric overlay. It was most encouraging that the Patent Office allowed us such broad claim coverage, as described in patent No. 6,194,912 (issued on Feb. 27, 2001) and in the 11 subsequent patents issued to my new company, eASIC.
I have spent many hours bringing this programmable ASIC technology to the market, using all my past learning. The first lesson is that everything takes longer than anticipated, especially when it comes to disruptive technology.
My challenge was to find the golden path, where we could devote the time needed to develop the technology without the pressure to immediately build products and revenue. The solution was to reverse the order of what I had done in Chip Express. I started offering the technology as intellectual property (IP) for embedded configurable-logic applications and only later developed a complete structured-ASIC product family.
This decision had many implications. The technology should target standard CMOS logic processes. Initial funding should be raised from angel investors, since most VCs at the time didn't favor the IP model. We focused on a few big players to help define the product, emphasizing the core configurable-logic technology first. Later we would add the I/Os and block memories needed for a full structured-ASIC product.
Our first partner, STMicroelectronics, helped validate the eASIC technology value and drove us to develop implementation techniques and technologies that proved to be very useful. Once the technology was proven, I decided to share with our champion at STMicro-Michele Borgatti-the fact that our technology provides an even bigger advantage once it is used with direct-write e-beam lithography.
A bit of luck always helps. We found out that STMicro had already integrated a direct-write e-beam in its fab operations. ST was happy to use this equipment for the eASICore customization, eliminating cost and the time needed for mask fabrication. Later, we convinced Flextronics to partner with us on the rollout of the FlexASIC, a programmable ASIC product family.
The eASIC IP offering, which started as a development strategy, evolved to become a strategic move in our effort to make that technology pervasive. We have realized the strong disruptive nature of technology that embraces both an IP offering for the high-end market enabling programmable SoCs, and a structured-ASIC offering for the mainstream market enabling programmable ASICs.
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