Wednesday, March 1, 10-11am PST

Moderator: Richard Goering, EDA Editor, CMP Media Electronics Group

Sponsors: Cadence and Infineon

Silicon at 65 nm, 45 nm and below can offer unprecedented integration, but the design challenges are significant. Changes on the process side may require new design techniques and tools. Design for manufacturing (DFM) will be an imperative, and the need for statistical timing and power analysis will grow. Every tool will face capacity challenges, and integrated design environments based on common data models will become crucial. What big innovations are needed in the next year or two to help us get to volume production at 65 nm, 45 nm and beyond?

Great Minds:
Chandu Visweswariah, Circuit and Interconnect Analysis, Design Automation, IBM Research Featured in Great Minds, Great Ideas.

Ted Vucurevich, CTO, Cadence Design Systems

Dan Page, VP Engineering, Synopsys

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Wednesday, March 8, 10-11am PST

Moderator: Rick Merritt, Editor-at-Large, EE Times

Sponsors: Analog Devices, Inc. and STMicroelectronics

The panel will explore the challenges and opportunities arising from the growing diversity of digital media sources. How do we measure what people actually use? What kinds of new gadgets may emerge rapidly or never get off the ground? What are some of the issues around content security? What role will technologies like watermarking play?

Ben Bajarin, Analyst, Creative Strategies

John Croteau, General Manager, Convergent Platforms and Services Group, Analog Devices Inc.

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