So to almost any technical conference on timing and chip design, and there you'll find Chandu Visweswariah, patiently explaining the benefits of statistical timing analysis and presenting the latest IBM Corp. research on the subject.

Visweswariah, who has spearheaded the work at IBM's Thomas J. Watson Research Center on this topic, believes that patience and persistence are the most important characteristics of an innovator. The soft-spoken Visweswariah embodies those principles, but he also carries with him a spark of enthusiasm as he discusses technology that he believes will be essential for next-generation chip design.

He may be right. Statistical timing analysis allows designers to account for silicon process variations, which become increasingly significant as feature sizes shrink. It also allows designers to predict how well a chip will yield at a given frequency. More than that, it represents a new way of thinking about design—one that embraces statistical probabilities rather than fixed numbers. As such, statistical timing analysis will require changes in the design flow and will compel silicon foundries to release statistical process information to designers.

Visweswariah's efforts in statistical timing analysis may help designers get working chips out the door at 65- and 45-nanometer process geometries without sacrificing yield or performance.