FinFETs for all
A second keynote on the second day of ISPD-14 was titled "Physical Design and FinFETs." ARM fellow Rob Aitken told the audience: "20 nanometer is the last bulk node, because it has too much leakage. FinFET is a replacement for bulk CMOS, but only for a short term of about three generations."
FinFETs are the best short-term replacement, Aitken said, but something else will replace them in about three generations. To make intelligent architectural decisions today, designers should be investigating FinFET replacements after 2020, because the solutions being considered by different foundries could lead to difficulties in terms of common tools and methodologies.
Global routing is usually not a good predictor for design-rule check (DRC) errors at the end of detailed routing. That led to this year's ISPD contest, which was evaluated by a industrial router by an EDA vendor.
(Source: Mentor Graphics)
Regarding the switch to FinFETs today, he described several physical design challenges, such as width quantization, complex fin rules for library cell designs, and pin accessibility. Double and triple patterning will make these issues especially difficult to resolve, risking the loss of advantages from process scaling if the correct physical design solutions cannot be found.
When FinFETs meet double or triple patterning, that's when we see even more standard cell layout problems. The double patterning elephant is already in the room. With power rails, we easily lose four tracks of internal cell routing. Custom layout is extremely difficult -- it takes much longer than you expect.
Aitken concluded by showing an example comparing the tradeoffs between area, speed, and power for a Cortex M3 design using an ARM process design kit with a 10nm predictive library with various combinations of litho and fin options.
ARM fellow Rob Aitken shows possible options beyond FinFETs
to continue Moore's Law.
The lead session on the third day was titled "CAD for Cyber Physical Systems." Professor Qi Zhu of the University of California, Riverside presented a talk on "Design Synthesis and Optimization for Automotive Embedded Systems."