Intel also used its 14 nm process to create what ISSCC organizers call the smallest SRAM bit cells reported to date. Intel’s 84 Mbit embedded SRAM sports high density cells that measure 0.050 μm2 and low power ones at 0.058 μm2.
TSMC will describe a new 16 nm 8 Tbit cell that takes “advantage of the relative PMOS-to-NMOS transistor drive ratio in FinFET technology, [so that] traditional NMOS write transistors in the bit cell are replaced with PMOS transistors,” according to the ISSCC program. TSMC also will show a PLL made in the process that consumes a total power of 9.3 mW at 200 MHz.
For its part, IBM will show a 1.1 Mbit embedded DRAM for processor caches made in its 14 nm FinFET technology. The 0.01747 μm2 cell sports a deep-trench capacitor and an array access time of 1.0 ns.
Samsung will describe two parts made in its emerging 14 nm FinFET process. A stochastic time-to-digital converter containing two delay cells delivers 1.17 ps resolution at 100 Msamples/s, consuming 0.78 mW and occupying 0.035 mm2. It also will show a PLL that dissipates 2.06 mW at 2 GHz and 0.8 V.
Among several chips geared to save battery life, ARM will present a Cortex-M0+ subsystem that consumes 11.7 pJ/cycle. It uses just 80 nW retention power, which ISSCC organizers says is an order of magnitude lower than previous sub-threshold designs below 180 nm.
Researchers at the University of Michigan will describe a 1.19 mm2 Cortex M0+ core consuming less than 295 pW from a solar cell. It is based on a new approach called dynamic leakage-suppression logic that consumes as little as 10 fW of active power per gate.
A handful of papers will describe Bluetooth LE transceivers that consumer 10 mW or less, including a chip from Dialog Semiconductor made in a 55 nm TSMC process. Robert Bosch will present a consumer gyroscope chip that consumes three times less power than the state-of-the-art, the ISSCC program says.
In high-performance processors, Intel will detail the Haswell version of its Xeon processor that packs 5.56 billion transistors into a 663.5 mm2 die. The 22 nm chip sports 18 dual-threaded x86 cores and 45 MByte L3 cache.
AMD will disclose Carrizo, an integrated processor with its latest x86 core. The 28 nm chip measures 244.62 mm2 and packs more than 3.1 billion transistors. Its new Excavator core is 23% smaller and uses 40% less power than AMD’s previous x86 core.
For its part, IBM will describe its latest mainframe processor. The 22 nm chip packs into a 678 mm2 die eight dual-threaded cores and a 64 MByte unified eDRAM L3 cache running at up to 5 GHz. IBM will also describe a hot-water cooled microserver compute node the size of a memory module based on a 1.8 GHz CPU with 48 GBytes DDR3 DRAM.
Kinam Kim, president of Samsung Electronics, and Sehat Sutardja, chairman and chief executive of Marvell Technology Group, will keynote the event.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times