Finding the right resist materials is one of the last big challenges for getting EUV into production. So far, researchers only get edges smooth if they use EUV exposures above a 20-millijoule/cm2 target.
A handful of companies, including ASML, Tokyo Electron, and ASM, are developing proprietary — read: expensive — techniques to resolve the issues. They generally involve resist treatments and process steps to etch or anneal away roughness.
“The smoothing techniques look very promising, so we feel confident that we can fix line-edge roughness,” said Steegen.
Separately, Imec is developing a pellicle to protect EUV wafers from contamination. It uses carbon nanotubes to provide the strength needed to withstand EUV exposures above 200 W while not preventing most of the light to travel through to the wafer.
Beyond EUV, the next big hurdle is a transition in the design of the basic transistor, the electric switch at the heart of any device. “How long FinFETs scale is a key question that needs to be resolved,” said Steegen.
So far, research indicates that FinFETs can be used at 5 nm, and if all goes well with EUV, maybe even at a 3-nm node. “At the 3-nm node, FinFETs and nanowires perform almost equally well, but nanowire gate pitches offer more scaling,” said Steegen, showing research on a stack of eight nanowires.
Next page: On track scaling and memories
A detailed look at resist issues shows efforts with versions that use chemical assistance and those that don’t (CAR and NCAR). LWR/LCDU refers to measures of line-edge roughness that should be no more than a tenth of the feature pitch size, in this chart a range of 3.2 to 2.6. Click to enlarge.