Timothy Keulenaer (left) and Arno Vyncke (above) helped design two tiny ASICs that fit on the end of an active cable (below). The transmit-and-receive chips merge four of today’s 25G lanes into a single 100G serial link for the fat pipes inside data centers.
Their startup, BiFast, thinks that it has a leg up on larger, established rivals. For example, Texas Instruments uses equalization rather than reducing the number of copper cables. InPhy and Macom focus on 56G links, not 100G ones.
The Ghent university grads travelled to DesignCon in Silicon Valley earlier this year to tell their story. They are seeking both design wins and investors.
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