Autonomous cars, for example, will implement a system with both high-performing CPUs and a separate hardware acceleration unit (whether GPU, FPGA or dedicated hardware) to run Artificial Intelligence. MIPSI6500-F comes with hooks and features that will the use of such heterogeneous computing.
Dominique Bonte, a managing director and vice president at ABI Research, noted that “multi-threading and shared virtual memory,” as highlighted by Imagination are the keys “to facilitate communication within heterogeneous architectures (between CPU and AI hardware accelerators)."
More specifically, Mace discussed the advantages of I6400/I6500’s Level 2 cache and coherency manager. IO Coherence Units (IOCU) provide low latency, dedicated connections for accelerators, while Shared Virtual Memory allows accelerators to work with CPUs faster and more efficiently.
(Source: Imagination Technologies)
Asked about the advantage of the MIPS I6500 architecture, Jim McGregor, principal analyst and founder of Tirias Research, cited its “ability to have many secure virtual execution environments for each cluster, many more than other processor architectures.”
He noted, “This is valuable because of the need to keep each functional area of the vehicle secure but interconnected. The large number of cores could also be used for sensor fusion and AI processing, but more commonly this is being performed by dedicated accelerators like GPUs and DSPs.”
Imagination claims that its I6500-F is designed to meet requirements for the ASIL B(D) level.
Automotive Safety Integrity Level (ASIL), defined by the ISO 26262 standard, identifies four levels of risk classifications from ASIL A to D, with ASIL D representing the highest integrity requirements.
So, what does the parenthesis in ASIL B(D) mean? Mace explained, “By the time when I6500-F IP is integrated into an SoC and its package is handed over to its customers, the system can be qualified up to ASIL D level.”
Mace stressed that I6500-F IP was “developed as a Safety Element out of Context (SEooC) with a safety lifecycle.” That was accomplished “with a strong collaboration with lead partners and together with a common independent safety assessor, ResilTech S.r.l.,” the company explained.
Asked if other processor core IP vendors also provide SEooC, Mace said he isn’t aware of any. ABI Research’s Bonte noted SEooC “offers more flexibility in terms of reuse, integration, and system certification.” He added, “It also allows Imagination to fully optimize their IP for functional safety.”
Imagination said that it is implementing “fundamental safety technologies across the MIPS portfolio, building on existing work with IP cores including the MIPS P5600.”
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