Using its 22nm SOI technology with 15 metal layers, IBM packed 12 upgraded Power cores, each with its own integrated voltage regulator and 96 MBytes shared L3 eDRAM on to 650mm2 chip. It draws about as much power as the previous chip and runs at about the same 4.5 GHz but delivers 60 percent better single-threaded performance, said Jeff Stuecheli, an IBM hardware architect (above).
IBM resurrected for Power 8 an earlier technique of an off-chip L4 cahce, in this case using 128 MBytes eDRAM. Stuecheli said he has racks of systems up and running in the lab.
The chip integrates PCI Express Gen 3 interconnects using a new Coherent Accelerator Processor Interface. The protocols will be available to third parties through a new Power Open program so they can design FPGAs and ASICs that link directly to the CPU. Unlike Intel's Quick Path Interconnect, CAPI does not need to carry memory coherency information because that's all handled by a block on the Power 8.