Even if the throughput problems are resolved, EUV still needs new materials to get chemically amplified resists into spec. In addition, engineers still need to develop a pellicle to eliminate mask defects, Ronse added. The highly complex and ambitious EUV systems have been delayed more than seven years, originally targeted for use in 2007.
Nevertheless the Imec expert expressed some optimism given the latest results. "There's quite a ways to go, but there's been progress," he said.
In February TSMC reported it could only make about 10 wafers/hour from its EUV system, which was dogged with reliability problems and had a light source running at just 12 W.
"I am much more optimistic now because customers are very happy with the improvements of the last three months," said Ronse.
Uptime has doubled to about 20% since TSMC's February talk, and ASML has a system in its lab that could run an 80 W light source by the end of the year, Ronse said. It hopes to hit "160 to 180 W by the end of next year, and that's really sufficient for high-volume, cost-effective manufacturing."
Intel signaled some time ago it sees a cost effective route to 10 nm chips without EUV. However, it is not saying how it would reduce the need for triple or quad patterning.
Without EUV, "there is no real Plan B," said Ronse, noting the complexity and costs of alignment, focus control, and optical proximity correction with triple and quad patterning. "No one will tolerate these costs -- you are not on Moore's Law anymore."
"It is not clear the scaling economics of Moore's Law will continue to deliver better, cheaper transistors," said Aart de Geus, co-CEO of Synopsys, in a separate talk here. "It's possible the semiconductor industry's drive going forward will not be from the supply but the demand side.
"So what if silicon becomes more expensive? The cost of certain pieces may go up -- I understand this is a contrarian view, but hope is eternal."
Next page: 450 mm wafers delayed