Lattice Semiconductor Corp. has added yet another voice to the in-system programming and boundary scan test standardization debate.
The Hillsboro, Ore. PLD supplier said that is has demonstrated for JEDEC a new technology that allows a single programming file to program multiple ISP devices from any supplier. Using the ispVM, or Virtual Machine engine, a 128-macrocell device from Lattice can be programmed in three seconds, Lattice claims.
The JEDEC standards committee is reviewing the proposal, but a vote is not expected for some time.
Both JEDEC and IEEE have been trying to come up with a standard for ISP programming and test for the past two years. Two competing proposals from Altera and Cypress Semiconductor (Jam), and Xilinx (Java API) are currently on the table. However, one is inefficient, the other too generic, according to Stan Kopec, Lattice's vice president of marketing.
Furthermore, the Java API proposal by Xilinx would impose licensing fees on users, and its evolution would be controlled by Sun Microsystems.
"A real standard must be both technically superior and commercially viable," Kopec said. "The ispVM solution has none of the technical or commercial baggage that the Jam or Java solutions have."
Using a virtual machine, rather than an interpreted language, minimizes programming time. The ispVM solution also features small device files and small player size for simple, uniform implementation, and supports low-cost 8-bit microcontrollers, Lattice said.
ispVM will be incorporated in the next major release of Lattice front-end design software, due out later this year. The company does not plan to market support for competing PLDs yet, but has demonstrated feasibility for it, according to Kopec.