A flip-chip packaging standard needed to spread the acceptance of integrated passive devices (IPDs) was finally set at a recent Electronic Industries Alliance (EIA) meeting by passive-component industry executives with the P-10 Integrated Passive Device Engineering Committee.
IPDs, which also include chip arrays, can contain several types of components, including capacitors, resistors, inductors, and diodes, in one package. Most industry insiders consider flip-chips to be a type of chip-scale package in which the IPD is designed with leads that are terminated on one side, allowing it to be mounted face down to the required interconnects.
"The combination of integrated passive devices with wafer-level, chip-scale technology will provide the industry with the smallest-form-factor, highest-performance, and lowest-cost platform, said Jan Konijnenberg, business unit manager for Philips Integrated Passive Components, in a statement. "With outline and footprint standardization, widespread industry acceptance will come at a much faster pace."
There has been a strong move toward the use of silicon substrates or thin-film-on-silicon technology in IPD packaging development, a move driven primarily by wireless-communications, PC, and portable-product OEMs. The devices are currently housed in conventional semiconductor packages such as QSOPs, TSOPs, and SOICs.
The group first approved the flip-chip packaging standard, dubbed EIAPN:4381, for layout and configuration, according to Jeffery Kalb, president and chief executive of California Micro Devices Corp., Milpitas, Calif.
"There are [now] standards for the layout of the pins, ball sizes, and pitch of the balls," said Kalb, who also chairs the Integrated Passives Market Council of EIA/ECA.
The key issue with flip-chip packaging is that it is possible to have a wide variety of pad and pitch variations, Kalb said.
"What this document does is lay out the guide lines for controlling the proliferation of variations. There's quite a bit of latitude associated with the specification, but it does start to bound the problem and offer some consistency in the way these devices are designed." Guidelines for the EIAPN:4381 standard have already been circulated among committee members, Kalb added.
"The committee is trying to determine grid-array dimension, pitch, and ball size, specified as a standard without restricting chip-scale packaging to any one approach," said Harry Van Wickle, chief executive of Fremont, Calif.-based Intarsia Corp., a joint venture between Flextronics International Ltd. and Dow Chemical Corp., which designs and manufactures integrated electronic components for digital and RF markets.
Many IPD suppliers believe that chip-scale will be the package of choice in the future because it provides a significant reduction in size and consumes less space than any other alternative.
Early adopters of IPDs in chip-scale packages will be looking to reduce cost and size, as well as improve performance, Van Wickle said. Chip-scale packaging, however, offers OEMs many different solutions, making it difficult to choose one until common specifications are established.
With more than 50 different chip-scale packaging technologies under development, the need for high-volume, low-cost solutions in standard outlines is growing, according to Jim Young, vice president of business development at Intarsia.
Recently, Intarsia and Philips Integrated Passive Components, a business unit of Philips Components, San Jose, announced an effort to co-develop standards for IPDs in chip-scale packages.
Together, the companies plan to focus on developing standard peripheral and grid-array packaging outlines for use in future portable and handheld electronic devices.
"It's also important when there are two companies working very closely on standardization because that gives the customer a little stronger comfort level for multiple sourcing," Young said.