Ultrasmall chip-scale packages (CSPs) are enabling the proliferation of ever-smaller portable electronic equipment, but at the same time are increasing the potential headaches for OEMs and CEMs using the devices.
"Chip-scale packages immediately provide twice the capacity of conventional packages on a printed-circuit-board surface, and even provide advantages over flip-chip," said Alex Chen, a design engineer at contract electronic manufacturer Celestica Inc., at the IPC/SMTA Electronics Assembly Expo here last week.
"And while chip-scale packages can be incorporated with minor modification into existing surface-mount technology [manufacturing] processes, inspection is a challenge, and double-sided chip-scale package assembly requires more costly technology," he said.
CSP devices are defined as any semiconductor in which the package is no more than 1.2 times the size of the bare die. The most prominent use of the technology is in fine-pitch ball-grid-array packages, although not all FPBGA packages are CSPs, according to James A. Forster, engineering manager for the Interconnect Business Unit of Texas Instruments Inc.'s Materials & Controls division, Mansfield, Mass.
Many design engineers, OEMs, and CEMs have seen CSP technology as an answer to the longtime problems associated with using bare dice in end applications.
While placing bare dice directly onto multichip modules or PCB substrates provides the greatest opportunity for device density, the use of bare dice is inherently difficult due to the fragile nature of exposed semiconductors.
CSPs provide the protection of packaging while maintaining the smallest possible footprint, Forster said. Although CSPs currently represent only a small fraction of the total semiconductor market, their use is growing rapidly-from about 400 million packages this year to roughly 3.5 billion packages by 2000, according to Electronic Trend Publications, San Jose.
At present, more than 50 different CSPs are offered by more than 30 semiconductor manufacturers, increasing the challenge of finding standard ways to test and assemble the devices.
TI is now offering burn-in test sockets for use with CSPs. The company currently has about six basic sockets, and approximately three dozen variations when the sockets are outfitted with plug-in windows to accommodate specific device types.
TI so far is concentrating on sockets for testing devices with a 0.75-mm pitch, which is common in flash and SRAM products. The company plans sockets for the 0.8-mm pitch found in SDRAMs in 1999, and eventually sockets for devices with a 0.5-mm pitch, which includes TI's microSTAR BGA packages.
The test sockets use tiny dual-beam pinch contacts that apply between 15 and 20 grams of pressure to each solder ball on a BGA package to test the device while limiting the risk of deformation to surface areas.
TI also offers a burn-in board interposer that plugs into the burn-in test socket to fan out the 0.75-mm pitch to the more common 1.27-mm pitch used in many PCB applications.
Other companies also are seeking to address CSP issues. For example, at Minneapolis-based Gryphics Inc., president James Rathburn said the company next year will begin production of removable chip modules (RCMs) for high-performance microprocessors and multichip modules.
RCMs will allow a user of a CSP to plug the device into the module, and then remove or replace the device.
"This eliminates the known-good-die issue," Rathburn said. "If one of the devices doesn't function properly, simply remove and replace it."
The RCMs will be sold directly by Gryphics, and will be made available for licensing, he said.