Bringing the ideal of an entire electronic system-on-a-chip closer to reality-while calling into question the future of the PLD market-LSI Logic Corp. said it will offer programmable ASIC cores for its largest networking and telecommunications customers by next year.
Using the programmable cores will allow OEMs to put complex, cell-based chips into production sooner, even as they continue to work on a small portion of the design that today is typically handled by a separate 10,000- to 50,000-gate FPGA, the company said. But while LSI espoused the performance and economic advantages of an embedded solution over stand-alone FPGAs, the company said it won't directly target the traditional low- to moderate-volume PLD business of suppliers like Altera Corp. and Xilinx Inc.
The concept of a programmable SOC is not new, and in fact is being approached from various angles as a way to add flexibility to the design of multimillion-gate chips. But the use of embedded FPGA cores was thought by most designers to be a fairly distant prospect. LSI plans to implement the programmable cores in its existing G12 process, with beta silicon in the first half of 2000 and production volumes in 2001.
"Contrary to some analysis that shows it only makes sense to embed an FPGA at 0.13 micron or below, we can efficiently do it at 0.18 micron," said Danny Biran, LSI's vice president of strategic marketing, Milpitas, Calif.
LSI claims the FPGA cores will consume one-fourth the silicon area of a conventional look-up table-based PLD, because they are based on a more granular arithmetic logic unit that is closer in structure to what ASIC designers are used to working with. On a 100-square-millimeter chip, 50,000 programmable gates would consume only 10% of the die area, Biran said.
LSI is the latest supplier to enter an SOC cate-gory that Dataquest Inc. has come to refer to as application-specific programmable products (ASPPs). In 10 years' time, ASPPs will account for some 80% of all SOC revenue, according to Jordan Selburn, an analyst at the San Jose market research firm. Selburn believes the potential of ASPPs could have "catastrophic ramifications" for suppliers of conventional programmable logic technology.
"When you embed 10,000 or 20,000 programmable gates, a lot of the applications for PLDs kind of go away," he said. "It won't happen this year, next year, or the year after, but I think [PLD suppliers] will feel a pretty significant hurt five or 10 years out."
While not everyone agrees, a few PLD suppliers have taken it to heart, and have offered their technology to ASIC suppliers-with limited success. GateField Corp., for example, licensed its flash-based ProASIC to Infineon Technologies AG and Rohm Corp., which both plan to offer the technology as programmable cores. Royalties from designs to date, if any, have been minimal. Xilinx said it "aggressively" marketed its FPGA technology to ASIC suppliers last year, but had no takers.
Observers said the core-based approach will only be feasible for an elite set of customers that can spread the increasing cost of mask sets across millions of units. For low- to medium-volume designs, PLDs still offer the most flexibility and cost effectiveness, said analyst Bill McClean of IC Insights Inc., Scottsdale, Ariz.
"Customers that in the past wouldn't undertake an ASIC design won't necessarily move to an ASIC now," he said.In addition, market watchers said LSI will inevitably battle the same software demons that have kept others-including IBM, Motorola, and Texas Instruments-from succeeding in the PLD arena.
Nevertheless, programmability is seen as a key enabler of commercially feasible SOCs, and LSI said it considered several existing programmable technologies. But rather than trying to squeeze large FPGA blocks into its chips, the company has licensed its programmable capability from a Silcon Valley start-up called Adaptive Silicon Inc. The Los Gatos, Calif., company designed the FPGA core from the ground up to have a granular structure and flexible form factor that will allow it to be easily integrated in an ASIC flow, Biran said.
Implemented in 0.18-micron technology, LSI said the FPGA cores will consume approximately 6,000 gates per square millimeter of silicon, and about 0.13-??W/gate/MHz, while delivering up to 200-MHz performance.