SAN JOSE -- At the Microprocessor Forum here today, Analog Devices Inc. disclosed details of a new 16-bit digital signal processor (DSP) architecture that initially will provide up to 300 million instructions per second (MIPS) performance.
The ADSP-219x family of DSPs is code-compatible with the company's existing ADSP-218x family, but with enhanced performance density and system-level interfaces, said Kevin Leary, DSP program manager for Analog Devices in Norwood, Mass.
"Raw performance is not necessarily the most important factor for DSPs," Leary said. "Customers are not necessarily looking for raw MIPS performance, but are concerned with ease of use, performance density, and power consumption."
Key additions to the ADSP-219x family include a 64-location, 2-way set-associative instruction cache, and a six-stage instruction pipeline, twice the size of the ADSP-218x family. The ADSP-219x also incorporates ARM Ltd.'s advanced high performance bus (AHB), providing greater of ease of integration in system-on-a-chip designs, Leary said.
Over the next year, Analog Devices plans to introduce a single-core general-purpose DSP, a single-core device optimized for motor control applications, a dual-core device for G.lite xDSL and G3 cell phones, and a quad-core device for Internet gateway applications.
The ADSP-219x core provides up to 1.2 billion MAC operations per second. The core operates at 0.4 mA per MIP at 2.5 V, and at 0.15 mA per MIP at 1.2 V.