SAN JOSE -- Intel Corp. has branded its upcoming line of high-end 64-bit chips "Itanium," and the company will discuss more architectural details tomorrow in presentations at the Microprocessor Forum here.
Among the details likely to be disclosed are more examples of the parallelism of the chip, according to Ron Curry, director of marketing for IA-64 products at Intel. The Itanium architecture contains 128 floating-point and 128 integer registers, with 64 predict and 8 branch registers -- four to eight times the number used in competing RISC architectures, Curry said. The Itanium chip uses a 10-stage pipeline.
Additional features used to enhance the performance include improved error correction code (ECC) capabilities, plus what Intel calls an enhanced machine check. If the Itanium chip comes across an ECC exception several times in a row, the architecture could alert the operating system and firmware, Curry said
Intel has also abandoned the "L0" cache nomenclature. Instead, industry-standard level-1, level-2, and level-3 designations will be used, as in other microprocessor architectures. Off-chip level-3 caches up to 4 megabytes will be possible, contained as discrete SRAM within the module cartridge. OEMs will be able to add a fourth level of cache if they wish.
Advanced Micro Devices Inc., in Sunnyvale, Calif., is expected to respond tomorrow with details from its own 64-bit architecture.