Altera Corp. is working with its main foundry partner, Taiwan Semiconductor Manufacturing Co. Ltd., to develop advanced interconnect techniques that will give its programmable chips a speed boost to support ever more demanding communications-system requirements.
An eight-layer copper wiring scheme for a 0.13-micron lithography process is slated for volume production in 2001. The companies are also investigating the use of low-k dielectric materials, silicon-on-insulator, and other emerging techniques to further increase device performance.
Today, the companies will announce production of Altera's APEX devices using 0.18-micron line widths and two layers of copper interconnect. Initial runs have produced 400,000-gate devices with internal clock rates as high as 250 MHz, and die yields equivalent to TSMC's current aluminum-wire process, said Cliff Tong, vice president of corporate marketing at Altera, San Jose.
"Our need for access to advanced technology in whatever form-whether it's packaging, intellectual property, or, in this case, process-is driven by what we need to do to support the communications marketplace," Tong said. "If we can get the speed and functionality needed by communications applications, we believe customers will use programmable solutions [where they now use ASICs or ASSPs]."
According to Dataquest Inc., the trend favors programmable logic. The San Jose-based research firm projects the market for application-specific communications ICs (including ASSPs, ASICs, and PLDs) will grow from $16.9 billion in 1998 to $33.7 billion in 2003. PLDs are set to outpace the overall segment, as more systems require reconfigurability, Dataquest said.
The boost in clock speeds and power efficiency afforded by copper will enable PLDs to more effectively support high-bandwidth interfaces, such as PCI-X, double-data-rate SDRAM, Gigabit Ethernet, and wireless protocols, according to Tong.
Altera also continues to develop high-speed core and I/O technologies and advanced packaging techniques, all aimed at increasing PLD performance and functionality. But migrating to copper interconnects and tighter line geometries also necessitates new architectural approaches to support lower operating voltages and a denser metal pitch.
"PLDs are the most hungry [devices] in terms of metal layers," said Francois Gregoire, senior director of technology at Altera. "What we sell is interconnect-that takes a lot of metal."
As a result, foundries and PLD suppliers have forged close ties in recent years, and programmable logic has become a "process driver" at companies like Hsinchu-based TSMC and its rival, UMC Group. Meanwhile, PLD users are reaping the benefits of leading-edge wafer-processing techniques in the form of smaller die, higher density, and lower power consumption.
During the coming year, Altera and TSMC will run test products on 0.15- and 0.13-micron processes, using various levels of copper interconnect. According to Altera, the goal is to find the optimum combination of line width and metal density to take advantage of copper's performance boost.
TSMC said its 0.18-micron process with two copper layers will be in full volume production in 2001.