Intel Corp. is developing a new "quad-pumped" processor bus that is expected to reach a clock speed of 400 MHz when running in Intel's next-generation Foster and McKinley server microprocessors, according to industry sources.
Sources contacted last week at the Platform 2000 Conference in San Jose said the new frontside bus (FSB) will be common to both the 32-bit Foster and 64-bit McKinley, the latter of which is slated to succeed the Itanium processor.
Foster is expected to be unveiled late this year or early in 2001 and will be available with up to a four-processor configuration per server. The device will be supported by the new Colusa chipset, which sources said also is in development.
McKinley will debut next year as the full-production version of Intel's IA-64 architecture, after Itanium, which was formerly known as the Merced processor, is rolled out late this year. The new 128-bit bus will have double the width of Intel's highest current processor FSB, sources said.
The platform's basic bus speed will be 100 MHz, which actually is slower than Intel's 133-MHz FSB for the Pentium III. However, Intel will use new technology called "double pumping" to achieve a 200-MHz speed on the bus line, or "quad pumping" to reach a clock speed of 400 MHz, sources close to the company's development efforts said. The technique either doubles or quadruples the number of instructions issued at any one time, effectively allowing two or four times the total data speed on the line.
An Intel spokesman said the Santa Clara, Calif.-based company does not comment on unannounced products.
Intel, however, has already said that Foster and McKinley will use double-data-rate SDRAM as main memory. By the time the new Intel processors ship in the next few years, DDR module bandwidth is expected to exceed that of the PC2100 specification, which operates at 2.1 Gbytes/s. The slower base 100-MHz FSB will allow the transmission of double- or quad-pumped data without running into interference, reflection, or noise distortions, sources said, while allowing the base bus line to handle data at speeds up to 400 MHz.
Intel is dovetailing its pumping technique with its multiprocessor-server architecture, which will connect up to four Foster or McKinley chips on a common bus line. Sources said the common bus will handle instructions concurrently from up to four processors without one of the chips waiting for execution of its instruction and creating delays on the bus line.
In contrast, multiprocessor servers using Advanced Micro Devices Inc.'s Athlon use a separate point-to-point EV-6 200-MHz bus line to connect each MPU. The server chipset controls parallel operations among the multiple EV-6 bus lines. The architecture is scalable, according to the Sunnyvale, Calif.-based company, so more than eight Athlon chips can be linked for more sophisticated server applications.
Sources at Platform 2000 said the Intel and AMD multiprocessing server designs represent such a contrast that they are setting up what could amount to a dramatic market shootout when next-generation systems are launched.