SAN JOSE -- Xilinx Inc. is bolstering its Web-based development tool kit by offering atechnology that enables system designers to instantly create a high-speed
interface between its most advanced FPGAs.
Called SelectLink, the tool automatically generates customized Verilog source code and test benches for an interchip data channel, supporting an aggregate bandwidth of up to 80 gigabits per second on multiple pins.
SelectLink draws on standard features of Xilinx's Spartan-II, Virtex, and Virtex E families, such as delay lock loops (DLLs), block RAM, and programmable SelectI/O and SelectI/O+ technologies. SelectLink technology can be used to create a system that delivers throughput of more than 311 megabits per second per pin for bus widths up to 256 pins, said Xilinx.
SelectLink technology consists of two main modules. The transmitter module creates a data-width conversion FIFO that has different read and write buses with different widths. This provides an efficient way to funnel data from an internal bus to a narrower external bus, according to the
The receiver module reverses the funneling and data rate conversions performed by the transmitter module and performs necessary shifting of data to align it with the signal clock.
The SelectLink Technology tool is accessible from Www.xilinx.com/applications/slcv/selectlink.htm