In the fast-paced world of communications-system design, chip makers are learning that time is more precious than efficiency.
Even under increasing pressure to provide more gates and megahertz for less money, suppliers still say customers are crying loudest for time-to-market.
Heeding the call, LSI Logic Corp. and Altera Corp. have separately adopted on-chip bus architectures designed to let designers "plug in" multisourced IP cores and eliminate the laborious task of reworking the interface. The companies announced IP-bus support at this week's IP2000 system-on-a-chip conference in Santa Clara, Calif.
LSI said it will standardize its CoreWare IP library to the Advanced Microcontroller Bus Architecture 2.0 (AMBA), which processor vendor ARM Ltd. has championed as an open interface for connecting multiple CPU and peripheral cores.
Altera, meanwhile, has added Palmchip Corp.'s CoreFrame architecture to its library of third-party IP. According to the San Jose company, the CoreFrame bus will let its PLDs act more like system-on-a-chip platforms.
Although on-chip IP buses consume significant logic resources, some designers consider it a small price to pay for a shorter design cycle, said Murray Disman, an analyst at Information Associates in Menlo Park, Calif., and editor of Programmable Logic News and Views.
"There's an interesting trade-off being made between productivity, time-to-market, and silicon," Disman said. "A lot of people are giving up silicon just to move designs faster."
For LSI, the decision to standardize on an IP bus came down to making life easier for its customers-even if that meant losing its proprietary hold on ASIC relationships, said Bob Van Steenburgh, director of processor cores at LSI's communications products division, Milpitas, Calif.
"The challenge we see is, it's no longer just LSI Logic's IP that we need to address," he said. "Customers want to use our IP along with their own in a chip. But they want to design their IP to a standard so they can have the freedom to reuse it from one design generation to the next at any silicon vendor they choose."
If LSI can help OEMs get new products into the market quickly, it will go a long way toward increasing customer satisfaction, Van Steenburgh said.
"We're doing everything we can to improve time-to-market," he said. "But more important than getting the design done is getting the design done right the first time. We believe bus standardization is one thing LSI can do to achieve that."
Programmable logic can also benefit from a unified IP interface, according to Altera. The Palmchip partnership is the first that will enable multiple cores to be integrated on a single Altera device, according to Luann Stechert, program manager for the company's IP partner programs.
"In the past, we targeted point solutions like Reed-Solomon decoders," she said. "Now, with the APEX family, our PLDs are large enough to handle system-on-a-chip designs. We're proving that it does make economic sense to integrate multiple cores in a PLD," Stechert added. "And people are choosing PLDs more and more, purely for the time-to-market advantage."
Through Altera's Megafunction Partner Program, Palmchip will offer its PalmPak development platform, which consumes 25% of an APEX 20K400 device and requires a simple, small-gate-count interconnect, according to Melissa Jones, vice president of marketing at Palmchip, San Jose. The platform contains the CoreFrame generic bus interface, a CPU-MChannel, a DMA channel, a flash/SRAM memory controller, and a basic hardware/software verification test bench.
"This is new territory for us," Jones said. "We've been working directly with system OEMs and fabless semiconductor companies, but we're finding that many customers will turn to a PLD solution first."
Indeed, IP integration was slow to take off in the PLD arena, but is becoming much more prevalent as device densities increase, according to Disman. "ASIC designers are using big FPGAs for prototyping, and it's becoming more common to prototype with multiple cores," he said.
"And, of course, the PLD guys are hoping those designs never become ASICs," Disman added.
In the second quarter, Palmchip plans to introduce a development board featuring an APEX 20K400 for hardware verification of designs based on the PalmPak platform. Additionally, the company is making the PalmPak platform available for Simutech Corp.'s RAVE IP-verification system.
LSI said the high-performance AMBA bus integrates neatly with its ASIC design flow. The architecture supports bus widths from 32 to 1,024 bits, and has protocols supporting burst-mode transfers and split transactions. It's also widely used, vendor independent, and license- and royalty-free.
Being an ARM licensee, LSI has already developed a large base of AMBA-compatible IP around the ARM processor, and is converting its entire IP library -- including its MIPS and ZSP processors -- to the AMBA interface. Complete library support is anticipated by next year's rollout of the Gflx 0.13-micron process, Van Steenburgh said.