Taking its cue from PLD market leaders, No. 3 player Lattice Semiconductor Corp. is targeting its newest offerings at high-volume, cost-sensitive consumer and communications applications.
By combining Lattice's in-system-programmable (ISP) technology with the popular MACH CPLD architecture of Vantis Corp., the new ispMACH 4A delivers high performance, low power, and what the company says is industry-leading density for as little as $1 per part.
The new devices will compete directly with Altera Corp.'s MAX 3000A and Xilinx Inc.'s XC9500XL low-cost CPLDs, which offer similar features and pricing. But Lattice will use a 0.25-micron process shrink to squeeze more density and I/Os into a smaller silicon area, according to Steve Stark, director of component marketing at the Hillsboro, Ore.-based company.
"Using our E-CMOS technology, we've been able to achieve die sizes 20% smaller than competitive devices," Stark said.
The ispMACH 4A family offers eight density options from 32 to 512 macrocells, with a SpeedLocking architecture that delivers up to 5-ns pin-to-pin propagation delay and 182-MHz performance. In addition, a programmable speed/power feature allows power consumption to be cut in half on logic paths that don't require the fastest possible switching speeds.
All densities support 3.3-V core operating voltage and mixed-voltage I/Os, with a 5-V core voltage available on the 64-macrocell part.
Packaging options feature PLCC, PQFP, TQFP, and BGA configurations from 44 to 388 leads. BGA packages include fine-pitch and chip-array options to reduce board space up to 70% compared with standard BGA technologies.
Priced in any volume, the ispMACH 4A3-32, -64, -128, and -256 devices are $1, $1.95, $7.75, and $17.75, respectively. Remaining family members are slated to be released midyear, Lattice said. Tool support is available through Lattice's newly released ispDesignEXPERT.