Continuing its drive into high-end networking and communications applications, Fujitsu Microelectronics Inc. today unveiled a 0.11-micron ASIC process, which the company said is capable of wiring up to 56 million gates on a chip.
The process, which uses five to eight layers of metal, features copper interconnects on all layers combined with low-k dielectric techniques to decrease transistor capacitance and allow faster chip speeds.
FMI, the San Jose-based semiconductor division of Fujitsu Ltd., will feature the technology in two ASIC series: the high-density, low-power Standard Cell CS91, and the quick-turnaround Embedded Array CE91 for high pin-count devices and those geared toward portable systems.
"The new ASIC series and technology provide our customers with extremely fast, high-density products with very high pin counts, along with a large array of cell libraries, macros, and IP cores," said Ryusuke Hoshikawa, president and chief executive of FMI. "We will be moving aggressively to bring our initial products to our leading customers in Japan and in North America quickly and efficiently."
Fujitsu is the latest ASIC supplier to tout a next-generation process that uses advanced interconnect techniques, joining IBM Microelectronics, LSI Logic, and NEC Electronics. Of the industry's top five players, only Lucent Microelectronics has yet to tip its plans beyond 0.18-micron.
Although Fujitsu's new process is still a year away from production, it looks to be a competitive offering, based on the combination of libraries, all-copper wiring, and low-k materials, noted Bryan Lewis, an ASIC analyst at Dataquest Inc., San Jose.
Both the CS91 and CE91 will feature high-performance analog elements, such as ADC, DAC, and op amps, as well as memory compilers for single- and dual-port SRAM, ROM, and register files. Initial design libraries-including basic gates, initial I/O options, some memory blocks, and mixed-signal macros-will be available by the end of this year, with the full library release containing high speed elements and special-purpose I/Os due by the third quarter of 2001.
In anticipation, the company is beefing up its ASIC design center support in Dallas, San Jose, and Raleigh, North Carolina, said Badar Baquai, vice president of FMI's Systems Solutions group.
An embedded DRAM offering, the CS90DLS, is planned by mid-2002. The process is expected to pack more than 192 Mbits of DRAM per 100 sq. mm of die area, with SDRAM clock frequencies of 200 MHz, and Fast Cycle RAMs exceeding 300 MHz.
FMI's 0.11-micron process will produce gate voltages of 0.85- to 1.65-V, with analog and I/O blocks being developed in both 2.5- and 3.3-V.