SANTA CLARA, Calif. -- Intel Corp. has delayed the launch of its 815 or Solano chip set from June 5 until June 19, according to sources close to the chip maker.
It is not yet clear whether the delay indicated a road map revision or a technical flaw with the chip set. Lately, Intel has delayed certain Xeon microprocessors to maximize yields and satisfy its OEM customer base.
The 815, however, is seen as an important product release for Intel because it mixes a native interface to PC133 SDRAM with the latest performance-enhancing features that OEMs covet.
While the 815 is targeted at the low-end "value" segment of the PC market, it will support both the 133-MHz front-side bus of the Pentium III plus the 66- and forthcoming 100-MHz bus of the new Celeron microprocessors that use Intel's Coppermine core. A source confirmed that Intel is de-emphasizing support for the older, 0.25-micron Mendocino versions of the Celeron, long prized by hobbyists that overclock the chips to faster frequencies.
A spokesman for Intel in Folsom, Calif., declined to comment on the release date or specific features of the forthcoming chipsets, as they have yet to be formally announced. He did say, however, that the 815 will support both the Celeron and Pentium III product families.
Intel has delayed two chip sets from June 5, the Intel 815 and the Intel 815E. The latter differs from the 815 in that it uses the second version of Intel's I/O Controller Hub, or ICH-2. According to previously disclosed road maps, the ICH-2's key feature is its inclusion of the ATA-100 storage interface.
However, no problems with the ICH-2 have been reported, and the first new chip set to use the technology, a derivative of the existing Intel 820 or Camino chip set, is still on track to launch on June 5, sources reported. The Intel 820E, as it is called, uses an interface to Direct Rambus memory.