WASHINGTON -- Something you wouldn't expect to hear at the Intel Developer Forum later in August but will: Intel executives recommending single-data-rate SDRAMs for the company's next-generation IA-32 and IA-64 processors.
At the same time, double-data-rate (DDR) SDRAMs will get scantnotice at the IDF, scheduled for Aug. 22-24 in San Jose. Instead,
Intel Corp. plans to showcase its broad push into the networking and telecommunications markets, while the company's traditional processor and memory road maps will be
scoured closely for clues to Intel's shifting business strategies.
Pat Gelsinger, vice president and chief technology officer of the
Intel Architecture Business Unit, said in a pre-IDF briefing this past week that SDRAM will play a role in the upcoming Pentium 4 in what he defined as "price point" markets.
Gelsinger reiterated Intel's position that Direct Rambus DRAM is
still the company's preferred memory for the Pentium 4-which
sources said will debut later this year as a high-end Direct
RDRAM-only CPU for workstations and top-of-the-line PCs. A
version for the midrange market that will include support for
SDRAM is expected to follow in 2001, according to industry
sources familiar with Intel's processor road map.
This runs counter to Intel's stance at the last IDF six months ago,
when Direct RDRAM was positioned as the only feasible memory
for the Pentium 4. Intel executives at the time said PC133 SDRAM
with a peak 1-GHz/s data rate was a mismatch for the 3.2-GHz/s
capability of the new IA-32 Pentium chip.
Gelsinger, however, said, "For many price points, PC133
SDRAM can still offer performance benefits with Pentium 4. The
high cache memory [included] with Pentium 4 ameliorates the
[data rate] difference with SDRAMs. It makes a slow memory look
Michael Fister, vice president and general manager of Intel's
Enterprise Platform Group, said the fourth-quarter launch of the
company's first 64-bit processor, the Itanium, will receive the
spotlight at IDF. Fister dismissed analysts' claims that the Itanium
is merely an entry point for Intel, and would be superseded by the
64-bit McKinley in the fourth quarter of 2001.
"We're planning an aggressive ramp-up for Itanium," he said. "It will
allow adopters to deploy their technology and gain expertise and
experience. These end users will then be in position to transition
quickly to McKinley a year later."
Gelsinger confirmed that the Itanium will not offer support for Direct
Rambus memory, but instead will run only with single-data-rate
SDRAM-and 100-MHz PC100 SDRAM at that.
The server market for which Itanium is targeted can achieve the
desired memory bandwidth by ganging together large numbers of
inexpensive PC100 chips, said Gelsinger, who declined to discuss
how Itanium, with PC100 memory, would compete against new
servers coming onto the market in the first quarter of 2001 that are
expected to feature DDR SDRAM running at about 266 MHz.
In fact, DDR SDRAM is not expected to receive much attention at
IDF. The updated Intel memory road map to be unveiled at IDF
won't show a DDR chipset until mid-2001, when the first IA-32
Foster processor for the enterprise server market is unveiled,
according to sources.
The Itanium's PC100 memory support has to be something of a
disappointment for Intel, according to Nathan Brookwood, an
analyst at Insight64, Saratoga, Calif. The Itanium fell victim to
chronic delays as Intel fought to move the 64-bit architecture out
the door, Brookwood said.
"When Itanium [then code-named Merced] started development
three years ago, PC100 wasn't even in the market and Direct
Rambus was then in the distant future," he said. "At that time,
PC100 looked like a good choice, but has now been far overtaken
by rapid technology growth in the market."
Intel executives in Santa Clara, Calif., said that half of the IDF sessions will be devoted
to 32-bit and 64-bit platforms, with the remainder focused on
software and networking and wireless applications.
IDF has been moved to the San Jose Convention Center and
surrounding hotels, having outgrown its traditional Palm Springs,
Calif., venue. Matt Haller, Intel platform evangelist, said attendance
is expected to jump 66%, to 5,000. The number of technical
sessions will double to 260, and exhibits by Intel partners will jump
from 100 to 170.