SANTA CLARA, Calif. -- Intel Corp. today abruptly terminated its much-touted Timna processor program. A spokesman for the Santa Clara chip giant said that trying to adapt the interface, originally designed for Direct Rambus DRAM, to support SDRAM instead ran into too many problems and would have impeded Timna's introduction.
Intel also said the sub-$600-PC price point targeted by Timna was now being met by its Celeron processor, the 810 integrated graphics chip set, and lower-cost motherboards. "Our customers told us they didn't need Timna to sell in this price range," the spokesman said.
Timna's demise means that Intel won't have an integrated on-chip Northbridge controller processor any time soon to compete with Transmeta Corp.'s Crusoe chip, National Semiconductor Corp.'s Geode MPU, or an upcoming offering from Via Technologies Inc. The Intel spokesman confirmed that no new highly-integrated processor is now under development, and Intel will rely on Celeron iterations to compete in the very low-end PC market.
The competing Transmeta and National chips vie for selected mobile or Internet-appliance portion of the markets, which Timna could have moved into. However, these rival chips did not target the low-end desktop PC market that was to be Timna's main thrust.
Timna's death also spelled the end to Intel's abortive Memory Translator Hub. Intel confirmed it is dropping MTH, which was to have modified the Timna controller interface from Direct RambusDRAM to work with much less costly SDRAMs. Originally introduced as a memory alternative for the 820 and a version for the 840 Direct RDRAM chip sets, MTH earlier this year ran into technical problems, resulting in a crash modification effort. That forced a delay in introducing Timna, which also used MTH to
support SDRAMs. The Intel spokesman said further work was needed to fix the MTH, which could have further postponed Timna's launch beyond an acceptable time.
Intel will use the Timna resources and planned production capacity now to augment its Celeron and 810 chip set operations.