To secure its role in the system-on-a-chip arena, Taiwan Semiconductor Manufacturing Co. Ltd. has rolled out a series of standardized tools to help customers select the right design blocks.
Unveiled at the recent IP/SoC 2001 conference here, the new tools include an IP tagging system that automatically tracks intellectual property blocks as they go into fabrication, an IP qualification program, and a process to help customers evaluate design libraries.
"These developments represent a level of maturity in the foundry industry," said Andrew Moore, design services marketing manager at TSMC North America, San Jose.
Foundries have only recently come to the fore as manufacturing technology leaders. But with a growing emphasis on outsourcing every aspect of chip development, foundry companies have eagerly expanded their front-end capabilities to provide a complete infrastructure for SoC development by aligning their factories with third-party IP, design automation tools, and design services.
In the latest example, TSMC has adopted an IP tagging standard defined by the Virtual Socket Interface Alliance that tracks the IP its customers put into production. Combined with TSMC's Total Order Management system, it will allow the foundry's IP partners to keep accurate tabs on royalties while helping customers avoid costly mistakes by identifying incorrect or outdated IP revisions before a mask is created, said Payman Kazemkhani, director of TSMC's IP Alliance group.
The tracking scheme embeds identification data into a previously unused layer of the design file that describes the chip design. TSMC extracts the data from that layer as it scans the design file in the mask-making process. The VSIA standard doesn't set up an IP protection mechanism, but because only the identification layer is scanned, there is no danger of the IP being compromised, according to Kazemkhani.
Another new tool offered is TSMC's 5-Star IP Alliance-a rating system for design blocks. Aimed at increasing user confidence in third-party IP, the tool categorizes IP from TSMC's partners as simulation proven (one star); works in TSMC silicon (three stars); or production proven (five stars).
TSMC said it plans to add ratings for manufacturability and testability based on VSIA design-for-test guidelines.
Taking the guesswork out of choosing design libraries, the foundry is also rolling out its Library 9000 Evaluation Flow, a selection guide to the characteristics and trade-offs of the libraries and memory cells TSMC offers for each of its process technologies. "We've found customers are not doing due diligence in selecting libraries for designs," said Colleen Muhal, library alliance manager at TSMC. "So we put together this flow to provide access to data ... so they can have confidence in the library they choose."
Similar to ISO standards, TSMC will categorize third-party libraries by Library 9000 compliance, which ensures completeness, quality, and silicon validation, Muhal said. Library 9000 compliance is complete for the 0.15-micron generation; 0.18- and 0.13-micron libraries are being evaluated, she said.