Updating its roadmap during last week's semiannual developers' summit, Intel Corp. said it is delaying the launch of its latest Xeon microprocessor for servers but is on track to unveil its first double-data-rate SDRAM chipset for the PC market early next year.
The release of the Foster-class Xeon MPU, a two- and four-way processor for dense rack-mounted and blade
servers, will be pushed back by three months to the fourth quarter due to a longer-than-expected chip validation, the company said during the Intel Developer Forum here.
The Foster is based on a quad-pumped- bus adaptation of the Pentium 4 and will follow a Xeon version for workstations unveiled in June that Intel is planning to upgrade to 2GHz this month.
The 32-bit Foster, which will use a third-party DDR chipset developed by ServerWorks, Santa Clara, Calif., will be succeeded next year by a 0.13-micron chip, code-named Prestonia, according to Abhi Talwakar, vice president and assistant general manager of Intel's Enterprise Platform group in Santa Clara. A four- to eight-way Xeon, code-named Galatin, will also be introduced in 2002 based on 0.13-micron linewidths, Talwakar said.
On the PC front, Intel said it will ship a DDR-enabled version of its 845 chipset, code-named Brookdale, to OEMs and motherboard makers in the fourth quarter to allow them to qualify the device for a gala launch in the first quarter of next year.
Intel has already qualified a number of DDR memory modules and its own 845 chipset, according to Louis Burns, vice president and general manager of Intel's Desktop Products group. Burns said OEMs and board makers need several more months to qualify the devices in their systems.
"When we introduce the 845 DDR chipset in Q1 '02, OEMs will be ready to deliver systems in massive volume," Burns said. "We expect to see significant performance increases for DDR" over single-data-rate SDRAM systems.
Burns said the DDR chipset requires significant testing and validation before its introduction. "It's not just a simple case of connecting a chipset to a processor frontside bus," he said, pointing out that the high-speed timing and sophisticated interfaces must be precisely designed and controlled in the chipset.
"We wanted to be certain that customers can mix and match DDR modules from any qualified vendor," Burns said, alluding to earlier incompatibility problems that kept DDR modules from different vendors from working together.