The frequency of errors in SRAM devices is intensifying as memory-IC vendors employ smaller geometries and continue moving their products into the networking equipment market.
A problem familiar to DRAM makers in the 1970s -- and largely resolved with packaging techniques-- soft error rates (SERs) are becoming more visible and troublesome for the $4 billion SRAM industry. A soft error is a missed operation, upset due to an alpha particle or cosmic ray. A memory misfire in a PC or cell phone, applications responsible for about half of last year's SRAM sales, often goes unnoticed by a user.
However, such a glitch in networking equipment, which accounted for about 24% of the 2001 SRAM market, can send information packets, such as money transfers, to the wrong address. As a result, error-correction and system reliability mechanisms need to become an automatic consideration of product architects, according to analysts and memory vendors.
Soft errors are a natural phenomenon. A burst of energy, caused by the collision of two atoms, follows a certain path until it dissipates, said Bob Merritt, an analyst at Semico Research Corp. in Redwood City, Calif. "If that trail happens to appear at the moment and space in time where the semiconductor is trying to measure what is being stored in that cell, the energy can cause the circuitry to read or write the wrong information," Merritt said.
The transition to 0.13-micron process technology is exacerbating SRAM SERs. "Soft errors are creeping in as the lithography gets smaller," Merritt said. "As the space gets smaller, it's easier to disrupt the process and to corrupt the data."
Other SRAM trends contributing to increased SERs include lower voltages, which reduce capacitance and increase a memory cell's susceptibility to alpha particles and cosmic rays; faster clock speeds, which give particles more opportunity to disrupt a read or write command; and higher densities, for which designers may fail to include adequate error correction or bit parity.
Although SRAM soft errors are not an everyday event, they are another variable systems designers should consider in new products along with target applications, price, voltage, clock speed, and die area, according to industry observers.
Soft errors are random and don't damage or destroy the chip, said Russ Lange, chief technology officer and a fellow at IBM Microelectronics, East Fishkill, N.Y. IBM provides customers with a tutorial and SER model to educate designers and assist them in deciding which tradeoffs (such as the inclusion of error-correction code) best fit their intended application.
"We have to work in detail with each customer to make sure they're aware of the phenomenon because many are not," Lange said "It's surprising how many have not thought through the issue."
DRAMs based on trench technology are largely immune to soft errors, but that means a tradeoff in access speed, he said. In some applications, using SRAM and building in error-correction code might be a better option. "It means a little bit more cost for a little bit more memory," Lange said.
The soft error measurement is failure-in-time, or FIT. A typical soft error rate is 1,000 FITs and means that one device will fail every 144 years, said Mark Eric-Jones, vice president and general manager of intellectual property at MoSys Inc., San Jose.
"Unfortunately, in 0.13-micron technology we're seeing some memory technology with error rates of 10,000 or 100,000 FITs per megabit," Eric-Jones said. "This brings the frequency of error in a single device down to weeks or months," Eric-Jones said.
MoSys has developed an error-correction technology that alleviates soft errors in its single-transistor SRAM without requiring more silicon area, he said. With the technology, dubbed transparent error correction, an error rate of less than 10 FITs per Mbit can be maintained in 0.13-micron linewidths, Eric-Jones said.
Another alternative, offered by Fujitsu Ltd. and Toshiba Corp., is fast-cycle RAM, which offers low latency and low failure rates, according to the two companies.
Cypress Semiconductor Corp. has attacked SRAM soft errors by incorporating improvements at the fabrication process, package, and die levels, according to Sabbas Daniel, senior director of quality in San Jose.
The company performs accelerated SER measurements prior to releasing products by placing radioactive sources in close proximity to the die, which accelerates the failure rates that would be observed under normal conditions, Daniel said. Cypress shares that data, on a device-by-device basis, with its customers. The company's goal for each product is a FIT of 200, according to Daniel.
"Depending on the application and the criticality of the application, the customer may choose to employ an error-correction code, if they feel the rate is too high," he said.
FITs can also change depending on the altitude, IBM's Lange noted. For example, IBM has discovered that SRAM tested at 10,000 feet above sea level will record SERs that are 14 times the rate tested at sea level, due to higher exposure to cosmic rays.
Although alpha particles can be controlled with improved packaging, such as a plastic coating over the die, cosmic rays can never be completely blocked out, according to Lange. "It's more or less a fact of life," he said.