SANTA CLARA, Calif. -- Three major DRAM makers -- Elpida Memory, Hynix Semiconductor and Infineon Technologies -- told the Jedex conference here Monday that they didn't plan to make 400-MHz speed memory in the DDR-I standard.
Samsung Electronics and Micron Technology within the last two weeks introduced DDR400 chips in the present DDR-I architecture. However, the remaining Big Five DRAM firms said they would wait for the next generation DDR-II standard to start sampling next year with 400MHz speed.
Joo Sun Choi, director of application marketing for Hynix Semiconductor America, San Jose, Calif., said trying to achieve 400-MHz with all its high speed challenges in the existing DDR-I standard "doesn't make sense."
Katsuyuki Sato, deputy general manager of technical marketing division for Elpida, said even if chip firms can make 400MHz DDR-I devices, it isn't clear that module vendors or motherboard suppliers would support such a memory.
Bill Gervasi, vice president and technology analyst for Transmeta Corp., speaking for many system users, claimed the DDR-I 400-MHz chip "will be limited only to a limited boutique applications." He felt the emerging DDR333 in DDR-I architecture would more than meet most user needs until devices in the next generation DDR-II standard reach market in the 2003-4 time period.
The first public details of DDR-II features dominated the Jedex technical sessions.
All five memory makers on a special Jedex panel agreed they will start sampling DDR-II with 1.8-volt capability in the first or second quarters of 2003 with initial mass production starting early in 2004. Sato of Elpida gave his firm's first roadmap showing engineering samples of DDR-II without on-die termination available in mid-2002, and with ODT sampling to begin in January of 2003.
The new devices will have on-chip termination (OCT) that will increase signal integrity by reducing impedance and noise that increasingly plays havoc with higher speed DRAMs. Jeff Janzen, senior DRAM applications engineer for Micron Technology, said OCT can also reduce parts count on motherboards by eliminating series resistors and voltage regulators and filters for a $3 to $8 savings per board.
DDR-II will also have off-chip (I/O) driver (OCD) calibration to allow adjustable impedance control for the first time. The real-time calibration is done in the chipset controller which sends commands to adjust the on-chip DRAM drivers, said Dong Yang Lee, senior manager of product planning for Samsung Electronics Memory division.
The next generation DDR chip also has a co-called posted CAS latency, a new technique to perform extra read-write functions within clock cycles. Transmeta's Gervaisi said posted CAS makes maximum use of the data bus, eliminates command bus collisions, and optimizes read-write operations.
DDR-II also has four-bit prefetch, twice the capability of present DDR devices. Gervasi said DDR-I with two-bit prefetch has nearly reached the limits of cycling the memory core at very high speeds. However, the DDR-II prefetch typically would allow 20 nanoseconds to cycle the DDR memory core, well within memory makers capability. Even the higher speed DDR533 would need only 15 nsecs core cycle time, about the same as DDR266 today.
Even as Jedex concentrated on DDR-II, the first hint was given of yet another generation DDR-III architecture with initial development in 2004. Elpida's Sato said DDR-III will continue to lower memory voltage levels initially to 1.5V with upgrades in 2006 down to 1.2V.