Having watched the average number of processors per SoC rise dramatically in the past year, Tensilica Inc. has designed its 350MHz Xtensa V core, slated to debut today, with the needs of multiprocessor designs in mind.
Statistics show that 59% of design starts using Tensilica's previous-generation Xtensa IV employed two or more implementations of the core-the average being 5.1, and the largest incorporating 18 Xtensa IV processors, according to Steve Roddy, the company's director of product marketing, Santa Clara, Calif.
"Most of the time, the implementations are different cores configured to do different stages of computation," Roddy said. "Xtensa V is all about how to put down multiple processors and hook them up in a single design."
The idea, he said, is to use task-specific processors as building blocks rather than employ the traditional "fortress-style, processor-centric designs."
To enable this concept, Tensilica has redesigned the Xtensa Local Memory Interface to bypass the usual bus interconnect, using instead a direct connection to daisy-chain CPUs. The boost in speed and efficiency can enable two 350MHz Xtensa Vs to do the work of a single multigigahertz core, Roddy said.
The company has also added a writeback cache option to reduce traffic on the processor interface, and a processor ID register to allow the system to easily differentiate between task processors.
Although Tensilica's claimed design-in success has yet to translate into trackable SoC shipments, adding support for multiprocessor designs could prove to be a wise move, said Tony Massimini, an analyst at Semico Research Corp., Phoenix.
"In the future, to improve system performance, it's going to take more than just ratcheting up processor speed. You've got to do parallel processing on the die," Massimini said.
It's also a way to increase per-chip royalties, particularly when the target market is characterized by low-volume designs such as communications infrastructure, he said.
The new Xtensa V features will be available in September. Licenses for the core, including a GNU-based tool chain, start at $350,000.