Synopsys Inc. announced at the Embedded Systems Conference in London that it will jointly develop and distribute with Hitachi Ltd. the first co-verification models of Hitachi's SH3-DSP and SH-4 RISC microprocessor cores.
Designers using the market-leading SH3-DSP and SH-4 core series will be able to reduce design cycle times of hardware/software co-verification using Synopsys' high-performance Eaglei hardware/software co-verification environment, according to the two companies. The models will be developed using the new Eaglei ModelLink development tool kit. The first models resulting from this agreement will be available in the third quarter.
"Our SuperH RISC engine family is widely used in the market for multimedia products and high-technology consumer products. They are in demand not only as CPUs themselves but also as system-on-chip cores," said Tadahiko Sugawara, department manager of the System LSI Business Division of Hitachi in Tokyo. "Synopsys has provided us with the important model-creation technology and support to help us efficiently meet the growing demand from our customers for access to the co-verification models they need for successful early integration of hardware and software."
"These cores are used in exactly the kinds of high-performance systems that demand the most advanced design and verification technologies," said Geoff Bunza, vice president of the Large Systems Technology Group at Synopsys (Mountain View, Calif.). "Together, Synopsys and Hitachi are giving designers the essential ability to successfully integrate the hardware and software portions of the design early enough to ensure maximum design quality and performance."