MoSys Inc. today is unveiling an intellectual property core that it claims will
quadruple the memory density possible using conventional embedded SRAM
technology without breaking the chip's space or power budget.
1T-SRAM-Q, the follow-on to MoSys' three-year-old 1T-SRAM cell, will allow
cellular handsets, digital cameras and camcorders, video games, and PDAs to
integrate up to 128Mbits of RAM (up from 32Mbits) using 0.13-micron process
technology, and up to 256 Mbits (from 64Mbits) using 90nm, the company said.
"This will change the way people look at embedded memory," said Mark-Eric Jones,
vice president and general manager of IP at MoSys, Sunnyvale, Calif. "It's not
just caches and buffers anymore. For a whole lot of systems, it's the main
The need for more memory bits on a chip is being driven by emerging applications
in consumer electronics and wireless communications that process, transmit, and
receive high-quality graphics at high speeds.
SRAM, the most common type of embedded memory, ordinarily requires six
transistors per memory cell, which consumes a lot of space and power as
densities increase. DRAM is more area-efficient, but also more difficult to
embed in a logic process.
MoSys designed the 1T-SRAM cell to provide DRAM-like density in a standard logic
process. 1T-SRAM-Q will offer the same cost structure, even though it requires
an extra mask and two additional processing steps, according to Jones.
"If 1T would occupy 10% of a chip, by switching to 1T-Q you've made the wafers
5% more expensive, but you're only using half the amount of silicon, so it's
break-even," he said. "If memory takes more than 10% of the chip, then you're
actually coming out ahead on wafer cost."
Most of the leading SRAM manufacturers now offer or are developing
single-transistor devices known as Pseudo SRAM (PSRAM). Typically, these are
stand-alone products designed to be drop-in replacements for discrete SRAM in
systems that need higher-density memory.
As much as 10% of applications that use SRAM are expected to switch to PSRAM by
the end of 2003, according to Pashupthy Gopalan, business unit director for
micropower SRAM at Cypress Semiconductor Corp., San Jose.
Cypress is co-developing with Nano-Amp Solutions Inc. a 1T-SRAM chip that is
scheduled for release in the first quarter of 2003. The product will primarily
target cellular handsets, which Gopalan estimated will represent 75% of PSRAM
MoSys' 1T-SRAM has made a small dent in the embedded-memory market, though
mostly in game platforms from Nintendo and Sony. Some 50 million chips have
shipped to date using the cell, generating approximately $15 million in
cumulative royalties for MoSys.
The 1T-SRAM-Q technology works by folding the gate oxide capacitor down the
transistor sidewall so that it occupies less horizontal area, but it does this
without disrupting metal layers or affecting logic transistors, according to the
company. To the designer, the circuit looks identical to 1T, but is half the
The cell includes MoSys' Transparent Error Correction technology, introduced in
January, to improve yield, reliability, and soft-error rates.
MoSys plans to tape out a 90nm test chip this month. It is working with
foundries and expects to sample the new technology in the second quarter of
2003. License and NRE pricing is the same as for the existing 1T cell.