SAN FRANCISCO--Fujitsu Microelectronics America Inc. unveiled a new fast-turnaround ASIC architecture designed to head off encroaching gate array and FPGA vendors in the high-performance, mid-volume market segment.
AccelArray, introduced this week at the Embedded Systems Conference here, uses 0.11-micron process technology to support 333MHz core operating speed and density up to 3.8 million ASIC gates, while pre-diffused embedded blocks cut design cycles from six months to two months, said Simone Shaghafi, product marketing manager at Fujitsu, Sunnyvale, Calif.
The first implementation is a general-purpose "Mega" platform with up to 1,128 I/O cells, 4.6Mbits of RAM, and 3.8 million gates that can use soft IP cores from Fujitsu's IPWare libraries.
Vertical market platforms are expected to be introduced starting in the fourth quarter of 2003. The platforms will embed pre-diffused I/Os, such as Fiber Channel, SPI-4, and XAUI, geared toward networking, storage, and industrial automation.
A similar product being promoted by LSI Logic Corp. known as RapidChip already integrates these high-speed I/Os, though it's built using older 0.18-micron technology, which would consume more silicon to do the same functions as a chip designed in 0.11-micron.
Analysts said more ASIC vendors are likely to follow this path as cell-based ASIC design costs skyrocket. FPGA and gate array vendors, too, are pushing up performance and embedding more functions to offer alternatives to cell-based approaches.
"Cost is king in this economy," said Bryan Lewis, an analyst at Gartner Dataquest, San Jose. "The market window is now open for new platform-based design products that enable systems developers to reduce their costs and move their products to market faster."
Fujitsu's AccelArray targets ASIC designs with typical volume between 5,000 and 100,000 units per year. Fujitsu claims its embedded flip flops, clock tree architecture, and libraries developed specifically for AccelArray cut power dissipation in half, compared to similar products.