Infineon Technologies AG and Micron Technology Inc. have released the specification for reduced latency DRAM II (RLDRAM II) architecture to target communications and data storage applications requiring fast random access with high bandwidth and density.
Designed for operating speeds up to 400 MHz, the RLDRAM II eight-bank architecture achieves a peak bandwidth of 28.8 Gbits/s using a 36-bit interface and a 400 MHz system clock. RLDRAM II provides a low latency and random cycle time of 20ns, speeding data throughput.
Additional advantages of the RLDRAM II feature set include on-die termination, multiplexed or non-multiplexed addressing, on-chip delay lock loop, common or separate I/O, a programmable output impedance, and a 1.8V core.
"RLDRAM II devices are an excellent solution to enable high-speed Ethernet and next-generation networking system designs to achieve up to 10 Gbit/s to 40 Gbits/s data rates," said Deb Matus, DRAM marketing manager for networking and communications for Micron, Boise, Idaho. "We continue to see more support for this technology throughout the market. "
Ernst Strasser, marketing director for specialty DRAM products at Munich-based Infineon Technologies, added, "The original RLDRAM devices offered a significant performance boost with unprecedented latency for high-speed networking designs. RLDRAM II devices take another step forward, advancing performance once again for communications products and other applications requiring very high speed random data access and exceptional bandwidth."
Infineon and Micron co-developed the RLDRAM architecture to ensure standardization, multiple sources, and functional compatibility.
RLDRAM II devices are available in a standard 144-ball FBGA, 11 x 18.5mm package to enable high-speed data transfer rates and a simple upgrade path from former products. They are available in 8 Mb x 36, 16 Mb x 18, and a 32Mb x 9 configurations.