Intel Corp. today will commence shipping its first Itanium 2 processor to be made in the company's 0.13-micron process technology. Called Madison, the chip hits 1.5GHz speeds and integrates a whopping 6Mbytes of Level 3 cache.
Madison will provide a 30% to 50% performance boost over the existing 1GHz McKinley chip with 3Mbytes of L3 cache, said Jason Waxman, director of multiprocessor platform marketing at Intel, Santa Clara, Calif. The numbers suggest Intel is seeing significant but diminishing returns on its strategy of winding up clock speeds and cache.
The company considers the Madison launch a milestone on the roadmap for bus-compatible CPUs laid out more than a year ago as part of its decade-long push to establish the 64-bit Itanium it co-developed with Hewlett-Packard Co. Madison will bolster the relatively slow uptake the very long instruction word (VLIW) architecture has faced in the server market to date, said Kevin Krewell, senior editor of The Microprocessor Report, San Jose.
Madison is "a solid offering, very competitive with the RISC CPUs, and HP is very committed to it," Krewell said.
Computer makers are only expected to sell about 32,500 Itanium-based systems in 2003, valued at about a total of $722 million, according to IDC, Framingham, Mass.
Itanium has been hampered to date by its large die size, high power consumption, and relatively poor performance on 32-bit X86 software, but Intel said it is addressing these areas.
Later this year, the company will introduce Deerfield, a low-power version of the Itanium 2 expected to have peak power consumption of about 65W, half that of McKinley and Madison. The lower power figures should help the chip get design wins in rack-mounted servers and server blades. Deerfield, also known as Low Voltage Itanium, will run at 1GHz, have 1.5Mbytes of L3 cache, and be made in 0.13-micron technology.
Intel also plans to release to operating systems developers before the end of the year a so-called IA-32 execution layer of software to translate X86 binary code into native Itanium code. The software would be available for Windows and Linux and ship as part of the operating system.
The software layer could provide up to a 2x speed increase on Itanium for some X86 applications, Waxman said.
At the high end, Intel said it will roll out next year a version of the Itanium 2 with the same processor bus and 9Mbytes of L3 cache.
The company said that it will support multithreading in the Itanium line, but has not yet detailed when or how it will do so. Because the 256-register VLIW architecture essentially requires an entire system to switch between threads and to provide a duplicate bank of registers, Krewell said "you might as well build two CPUs" as provide a multithreaded Itanium.
That's essentially what Intel is planning for 2005 when it launches its dual-core Montecito version of Itanium manufactured in a 90nm process. A mul- tithreaded Itanium is not expected to arrive until after Montecito.
Earlier this year, Sun Microsystems Inc. leap-frogged Intel and IBM when it announced plans for a multicore, multithreaded CPU handling as many as 32 threads. Sun said it will ship that chip, called Niagara, in 2005.
Krewell said that the Niagara chip could outshine all contenders in mainstream Web-serving jobs, while Intel focuses Itanium on tasks such as running large databases and high-performance computing.
"The thing I question is how widespread will Itanium become given its increasing focus on the small but profitable high end of the market," he said.
The 1.5GHz, 6Mbyte L3 Itanium 2 costs $4,226 in quantities of 1,000. A version running at 1.4GHz with 4 Mbytes L3 costs $2,247.