Any survival handbook for Silicon Valley start-ups trying to sell intellectual property might well include a final sentence that reads: If all else fails, build and sell chips yourself.
That's what one-time IP provider Leopard Logic Inc. plans to do late this year or early next year when it rolls out its "hybrid" programmable chips, mixing elements of FPGA and ASIC design.
The Cupertino, Calif., company willnot disclose all it has in store, but a quick glimpse puts it somewhere between off-the-shelf devices targeting vertical-market segments and fully programmable FPGAs.
"We're not going after FPGAs or ASICs head-to-head. We think we're moving into new territory," said Chris Phillips, president and chief executive of Leopard Logic. "I don't think the IBMs or Xilinxes have dealt with the issues we're bringing to market."
Founders of the 21-person company had envisioned developing an FPGA fabric that could run side by side with hardwired logic gates and then selling the technology to large chipmakers as IP. The company calls its FPGA technology sound, but has had a harder time emulating the IP business model of companies like ARM and Rambus.
The reasons have a familiar ring for would-be IP providers. When the chip market crashed, Leopard's investors lost confidence in the IP model, which tends to have a long gestation period. Also, the company admitted, chipmakers have been fussy about things like gate densities, which are worse for FPGAs than standard-cell designs.
But the company wasn't ready to give up, so about a year ago it changed course and became a fabless chip supplier. Its first 0.13-micron test chips, built by Taiwan Semiconductor Manufacturing Co. Ltd., were qualified two months ago, and Leopard has been working with "a handful" of companies to validate the design before production, Phillips said.
Leopard will not disclose product details, although it has said one version of its programmable chip will be for wireline networking, one for storage applications, and another for wireless gear. A generic platform will handle various applications.
To target these vertical markets, the company will have to embed some functions into its chips as hardwired IP. But, Leopard said, it aims to keep the chips as programmable as possible.
"The way I look at it is, we're trying to create configurable logic and you allow users to configure that logic in hard form and soft form," Phillips said.
By implication, users should then be able to evaluate performance and density characteristics of the logic as either FPGA or ASIC gates and then have a way to partition the chip accordingly. This differs from the approach taken by FPGA vendors and some ASIC vendors, which offer pre-diffused IP cores and surrounding logic gates that can be configured through a bit stream (for an FPGA) or as a metal mask option.
Leopard will have some catching up to do. Most major ASIC and FPGA vendors have already announced plans to go after chip designers who are looking for something that isn't as costly or as time-consuming as standard-cell design but who don't want to pay the high per-unit cost of FPGAs.
But Leopard calls many of these approaches inadequate for the kind of unit orders it is targeting, ranging from 5,000 to 50,000 chips. FPGAs are pricey, tend to have lower capacities, and are slower than ASICs. Conversely, mask programmable "structured ASICs" put too many restrictions on a designer, are not field-programmable, and still require back-end processing by the vendor, according to Leopard.
The company said it can offer the best of both worlds while keeping design restrictions to a minimum. Designers can work with industry-standard simulation and synthesis EDA tools, with the back-end tools accepting generic RTL rather than "stylized implementations," Phillips said.
Whether Leopard's hybrid approach will pass muster with potential users depends on factors that are still undisclosed, like how much of the circuitry is fixed and how much is flexible, and will they be continuously reconfigurable on the fly, or used like FPGAs for periodic design updates, said Jordan Selburn, an analyst at iSuppli Corp. in San Jose.
"I'm not surprised that Leopard had issues as an IP supplier--people have not figured out how to use a mixed FPGA/ASIC fabric," Selburn said. It might be an easier sell in chip form, provided Leopard itself handles the configuring, or supplies the software programming stacks to customers, he said.
Though it has made the transformation to a fabless chip supplier, Leopard is still willing to license its technology should the right opportunity come along. There is evidence that some major chipmakers are warming to the idea of embedded FPGAs.
IBM Microelectronics, for one, is planning to embed FPGA cores being developed by Xilinx Inc. for 90nm chip designs. And Samsung Electronics Co. Ltd. recently said it is exploring embedded FPGAs for ASIC and application-specific standard parts.
Additional reporting by Crista Souza