A small company has produced what analysts say is unique synthesizable IP--a collection of up to nine 8051-compatible processors that can operate independently or as a single unit under the direct supervision of the lead CPU.
The processor cluster from QuickCores IP, Pro8051-Hypercore, is available for synthesis into Actel Corp.'s Axcelerator or ProASIC-plus FPGAs, but is portable to virtually any synthesis environment, according to the company. It has applications ranging from increasing the integration of a multi-MCU system, to cooperative multiprocessing architectures, to fully fault- tolerant systems.
QuickCores IP began the development trying to solve a different problem, said company proprietor Jerry Harthcock. Initially, the project was to design a way to do completely hardware-based, noninvasive debug of an operating 8051 core implemented in an FPGA.
Rather than embedding either a monitor program in the software or a logic analyzer in the hardware, Harthcock modified the 8051 core logic so that an external 8051 could, in effect, communicate telepathically with the MCU core.
The external device could have access to all of the target 8051's resources, and could even fetch and decode an instruction that the target would then execute. All of these activities were designed to be completely transparent to the normal operation of the 8051 core, so that monitoring and debug operations could proceed without changing the timing of the MCU running its application code.
Meanwhile, Harthcock said, a customer of QuickCores became interested in integrating a number of the company's 8051 cores into a single FPGA.
While planning the best way to achieve high integration of multiple cores, and concurrently implementing the new debug capabilities, Harthcock decided the debug hardware might have use far beyond just debugging code.
The same capabilities that permitted one 8051 to debug another's operation made for a powerful multiprocessing environment, he said.
But for the space client in particular, the cluster had another capability. By using the ability of the master processor to look into the registers and memory of the target MCUs, it is possible to implement a tightly coupled redundant array for fault tolerance.
The master processor can check the work of the other processors or compare them against each other. If a discrepancy is detected, the master can correct the error, restart from a checkpoint, or switch in another CPU. It is even possible for one of the processors to be running a task that checks for failures in the master at the same time the master is checking everyone's work.
The range of possibilities far exceeds what is normally thought of as the application space of the 8051. Yet these capabilities are directly applicable to many jobs for which 8051s are often used. Hence the MCU cluster may be a viable alternative to moving to larger, code-incompatible processor cores, or even to the development of custom hardware, according to QuickCores.
An entry-level evaluation kit with a dual CPU version of the Pro8051-Hypercore, implemented in an Actel ProASIC Plus APA-150, is available for $499. The nine-CPU Pro8051-Hypercore, implemented in an Actel Axcelerator AX2000 is $3,000.