ARC International today will announce it has tweaked its configurable processor to run digital signal processing code faster while cutting the amount of power the device consumes in half.
The ARC600 processor core runs "worst case" at 290MHz, using the process technology of Taiwan Semiconductor Manufacturing Co. Ltd. and consuming 40µW/per MHz. Without cache memory, the core takes up 27,000 gates, making it one of the smaller processors in the market, according to ARC.
To boost performance, the company lengthened the pipeline from four stages to five, and changed the cache so it can be used as either a large virtual memory or RAM.
ARC also added an optional three-stage DSP pipeline, which appears as a preverified register transfer level (RTL) option in the company's design software. Using the DSP extension makes the core bigger, but allows designers to reduce the overall operating frequency.
Alternatively, designers can create up to 128 of their own instructions for the same job, a key feature of ARC's configurable processors.
"You have got certain levers you can pull to reach the balance that's important to you," said Edward Pazmino, product marketing manager at ARC, who is based in San Jose.
To reduce power consumption, the company said it has found a way to remove redundant cache memory accesses and has applied gated clocks to registers when they aren't being updated. The processor also retains the 32/16-bit instruction set architecture to reduce memory usage and power.
The core is being packaged in a way that isolates it from peripherals and the system bus, which ARC said should make it easier to pack more processors into one chip design. This CPU "island" includes a synchronous interface that can connect to BVCI and AMBA buses.
To verify the core, ARC said it has run compiler tests using FPGAs, tested for line coverage, and used cycle-accurate simulators to verify the RTL. Pazmino said the company is also considering working with structured-ASIC vendors to verify the core in silicon.
ARC said it is ready to license the core, which is binary-compatible with its current A5 processor. The company declined to disclose its licensing fees.