Crimson Microsystems Inc. will announce today its plans to take linecard integration to a new level using a chip that melds pointer processing and framing with control-plane functionality.
The announcement comes on the heels of a two-year period within the metro-access sector of regrouping with a back-to-basics mentality. Projects focused on delivering OC-768 (40Gbit/s) and even OC-192 (10Gbit/s) rates have been shelved in favor of design efforts that can squeeze more bandwidth out of existing architectures or more efficiently use the pipes in place--both of which have driven the development of services like virtual concatenation.
Aware of this trend, Deepak Rana, a former executive of Intel Corp.'s Optical Networking Division, formed Crimson in April 2001 to deliver a way to improve linecard integration and reduce cost in existing box architectures.
With funding of $12.5 million and a team that includes engineers from Alcatel, Cerent, Ciena, and Intel, Rana is bringing Crimson out of stealth mode and detailing how the Pleasanton, Calif., company plans to achieve its integration and cost goals.
To begin with, Crimson has developed what it calls a "microcommunication processor." Developed around a 250MHz, 32-bit Tensilica Inc. processor core, the architecture handles pointer processing, termination, transcoding, switching, and transmux functionality. At the same time, designers can tap into the configurable Tensilica core to handle control-plane processing tasks, a function typically relegated to a dedicated processor or card.
"Our entire product line fits in existing boxes and provides an exponentially lower cost," Rana said. "At the system level, our technology can lead to a 90% to 95% cost reduction."
The processor's on-board framer is rate independent, allowing it to support OC-3, OC-12, or OC-48, he said. The on-board switch is a nonblocking element that supports Sonet, SDH, or PDH traffic.
To complement its on-board capabilities, the microcommunication processor comes with a 10Gbit/s interface on the line side and dual 10Gbit/s interfaces on the system side, one for active schemes and one for protection. It also has a 2.5Gbit/s access bus that Rana said can be linked with off-chip FPGAs or ASICs that perform framing and other tasks.
One of the interesting features of Crimson's microcommunication processor lies in the company's ability to tailor the chip at the silicon level for a specific function.
According to Rana, this approach provides efficiencies for the company in the manufacturing process. By disabling certain functions, Rana said that Crimson can reuse the same die for different applications and leverage its silicon costs across multiple projects.
"We don't need to build five different chips," he said.
Crimson's first chip, called Ruby, is a 0.13-micron device that will sample in the first half of 2004 and will include all functions except termination and transmux.
The company is working on a second-generation 0.13-micron part, called Emerald, that will include transmux functionality. Termination capabilities will be added in the third-generation chip, Sapphire, which will be developed in a 90nm process, Rana said.
Crimson expects to start shipping Ruby in volume in 2005. The chip will be delivered in a 41 ¥ 41mm, 1,450-ball flip-chip BGA package and will draw 15W when configured as a cross connect and under 10W when configured as a framer.
The company said it is also working on raising additional funds in a Series B round.