Standard-cell designs under 'evolutionary' pressures
Cost pressures, changing requirements, and short design windows seem to favor programmable-chip solutions, but are ASICs becoming extinct? Not exactly.
A panel of experts gathered last week at the Network Processor Conference in San Jose said the industry is witnessing an evolution of ASICs, although what new form they will take is still up for grabs.
"Darwin was right," said Warren Miller, vice president of marketing for Avnet Design Services, a unit of distributor Avnet Inc., Phoenix. "What you see out there won't be a dinosaur anymore, it will be something else."
ASICs continue to dominate in network processing applications, not because they are the best solution but because OEMs have already done the design work and are reluctant to switch to a new chip architecture, said Allan Armstrong, an analyst at research firm RHK Inc., South San Francisco. But market forces are beginning to change that mind-set, he said.
A February 2003 survey by Avnet of 73 customers, primarily in wired and wireless communications segments, bears out what pundits and chip suppliers have been saying for some time, that the projected lifetime volume of designs peaks in the 1,000- to 10,000-unit range, that ASIC design cycles are unpredictable, and that market requirements constantly change.
"I believe the broad use of cell-based ASICs is over," said Robert Blake, vice president of product planning at Altera Corp., San Jose. "New pressures are changing the rules and opening up opportunities, mainly for FPGAs in the low-density space and structured ASICs in the high den- sity space."
The financial opportunity for "structured" approaches is sized by various sources between $2 billion and $5 billion. "That's stolen mainly from standard-cell ASICs, not FPGAs," said Doug Bailey, vice president of marketing at Chip Express Corp., Santa Clara, Calif.
Even so, structured ASICs have largely been identified with FPGA-to-ASIC conversions, leaving suppliers with a marketing dilemma. Some are clearly on the defensive with regard to reprogrammability, the one FPGA feature that ASICs can't compete with.
Reprogrammability is something that ends up on the bench in most mission-critical applications, said Majid Bemanian, senior director of marketing for communications products at LSI Logic Corp., Milpitas, Calif.
"You can value reprogrammability in all kinds of ways, but it's a very expensive cost," said Chip Express' Bailey. "FPGAs are great tools for prototyping and emulation, but you would have to be crazy to put one into production."
Others maintained that the need for flexibility favors programmable platforms. "A $5 billion industry can't be driven by a bunch of 'crazy' customers," asserted Krishna Rangasayee, director of vertical market strategy at Xilinx Inc., San Jose.
"I've seen a lot of projects go wrong because engineers got it wrong, but I've seen a lot more go wrong because the requirements changed," added RHK's Armstrong. "Programmability is something I think is fundamental to a lot of communication platforms' needs."
Stefan Tamme, vice president of sales and marketing at Leopard Logic Inc., offered that a hybrid architecture is needed that combines the best of FPGA and ASIC and casts off the limitations of each. As reported by EBN in July, Tamme said that start-up Leopard, Cupertino, Calif., is preparing a January launch of a product that fits the bill--though details have not been disclosed.
Armstrong agreed that ASICs have to change, but in the end they may take on many shapes.
"I believe that a lot of next-generation boxes will contain something other than ASICs," Armstrong said. "It could be ASIC-plus-FPGA or ASIC-plus-network-processor or something else, but some sort of hybrid architecture will be required."