FRANKFURT, Germany Indicating a trend toward soft cores in the system-on-a-chip era, VLSI Technology Inc. (San Jose, Calif.) plans to give customers the ability to customize cache memory for ARM microprocessor cores.
Bob Payne, strategic technology officer with VLSI Technology, said that next year his company will provide CPU Builder, software that provides a configurable, parameterized view of the ARM cache memory as part of its HDL System Builder design-support tool.
Payne disclosed the move at the IP98-Europe conference and exhibition held here this week.
VLSI Technology customers will be able to select exactly the cache sizes their applications need. Payne said that holding cache memories to the minimum necessary to support the chosen application would go a long way toward optimizing a system-level design for the lowest possible power consumption.
With CPU Builder, Payne said users will be able to click buttons to choose between unified or separate data and instruction caches, and to specify the number of data words per cache line, the number of ways of associativity, size of write buffering and overall size of the caches. Once the detailed features have been selected, a button will allow a VHDL or Verilog HDL file to be compiled automatically.
Suited for simulation
The HDL file could then be used for simulation with a model of the ARM CPU to help engineers optimize the cache size.
ARM has traditionally supplied its cores in "hard" form optimized for each semiconductor licensee's process technologies. ARM semiconductor licensees or ASIC customers have been able to design their own cache memories. But ARM has developed full processor versions combining its various series of CPUs with cache memories and memory-management units with limited flexibility, which have tended to be the architectures used by licensees.
Payne said ARM was aware of CPU Builder. VLSI Technology was the first licensee of the ARM core, a founding investor and is still a shareholder.
CPU Builder will be one aspect of VLSI's HDL System Builder software support for its ASIC customers, he said. The support will provide the ability to compile an RTL description of a system from a highly parameterized and forms-based view of the company's portfolio of IP cores and gate-level capabilities.