SAN DIEGO In its struggle to catch up with advances in microprocessors, the venerable PCI bus is becoming a push-me/pull-you, shifting into high gear and getting shunted aside all within one week.
On Wednesday (Nov. 11) Intel Corp. will unveil, here, full details of its vision of what lies beyond the Peripheral Component Interconnect, a technology it has generically dubbed next-generation I/O (NGI/O), and ask the PC industry to begin building products based on it. Meanwhile, the PCI Special Interest Group was expected to make a key move on Friday (Nov. 6) in its effort to ratify a life extension of PCI, called PCI-X, stretching the capabilities of the aging bus for several generations of new designs.
PCI-X could find a home in server and perhaps even desktop designs that hit speeds of up to 133 MHz and peak data rates as high as 1 Gbyte/second starting late next year. But NGI/O, which will not appear in systems until at least late in 2000, aims to start at 1.25 and 2.5 Gbits/s and to establish a new beachhead in PC data capabilities that could extend for years to come.
"We've seen 700 percent improvement in processor performance from the first Pentium to today's chips, but only 200 to 400 percent improvement in I/O performance," said Tom Bradicich, director of architecture and technology for IBM's PC server group. "These I/O problems were solved in mainframe computers before I was born. Nevertheless, bringing mainframe-class I/O to the PC server is a profound task."
That's the goal of NGI/O, which Intel will detail to a group of about 200 PC and add-in-card engineers from as many as 50 companies here this coming Wednesday. "We want to disclose to the broad industry everything needed to build products, and we want the industry to adopt this technology and start building products around it," said Mitch Shults, director of server-platform marketing at Intel (Beaverton, Ore.).
Intel will detail an architecture that uses the basic physical-layer techniques common to Gigabit Ethernet and Fibre Channel to link the host with target channel adapters that interconnect across a generic switching fabric. Host and targets can remotely control each other's memories using a new protocol.
Like its predecessor, PCI, NGI/O was largely defined from scratch by Intel and will be made available on a royalty-free basis. The specification to be released in the coming week will define connector, electrical and protocol aspects of the new data highway.
Key to the architecture is a new protocol that defines a packet-based system of variable-length cells with a maximum of 292 bytes per cell and a scheme for ranking cells by priority. The protocol, embedded in hardware at OSI Layers 2 and 3, is designed to enable end-to end system latencies of a few hundred nanoseconds.
Unlike a PCI bus structure, in which add-in cards access dedicated portions of system memory via the system processor, NGI/O uses separate host and target channel adapters that negotiate transactions. They use their own local memory pools, without slowing down a system CPU.
Intel intends to make the host channel adapters. Its first, dubbed the VXB, links to a so-called F-16 16-bit serial bus to a system memory controller. "We would sell that as part of our server chip set, but companies like Sun also could build them, linking to their own CPUs and processor buses," said Shults.
Intel expects a variety of companies will build switching ASICs for NGI/O that link the host and target channel adapters. To ensure interoperability, Intel will supply free of charge VHDL code describing key interface silicon for the switching ASICs. The company expects third parties to build target-channel adapters, which would ultimately be integrated with controllers for add-on devices such as Gigabit Ethernet, Fibre Channel or SCSI cards.
"We are working with [Intel's] i960 group in Chandler, Ariz., to create a set of integrated building blocks for people who want that," Shults said.
Creating the new generation of switch and adapter ASICs could take 18 months, pushing the first real deployments of NGI/O out to servers that will ship late in 2000. Shults would not detail which server and adapter-card companies are planning to build NGI/O products. However, he suggested some makers of high-end RAID, storage-backup and router systems will include NGI/O connections on their designs. He also said that multiple NGI/O connections could be bundled into very high-bandwidth architectures for applications such as HDTV.
While suitable for what Intel considers mainstream servers, NGI/O will also open the door to mammoth systems with as many as 64,000 connected devices. "That's the class of system we are trying to enable people to build," said Shults.
It's not clear how deeply major computer makers have bought into Intel's NGI/O implementation. Several system makers say they share Intel's general vision for future I/O, and Intel claims many companies will announce support for NGI/O in the coming week.
"It's early in this and we are still evaluating our technology options," said Bradicich of IBM, whose group now has S/390, AS/400 and RS/6000 engineers working on the issue of I/O for future PC servers. "We hope that we will be able to work together. There is no desire . . . to have a bus war."
The NGI/O disclosure follows the PCI SIG's initial approval of a working group to plan PCI-X. This life extension for PCI defines 64-bit versions of the bus at 66, 100 and 133 MHz using a new register-to-register data-transfer scheme.
Timing specifications for PCI-X will be challenging, said Warren Questo, chairman of the SIG. PCI timing of data through silicon from first valid clock to data out is now 4 to 8 ns and would become 3.5 to 2 ns under PCI-X. Across-the-board signal timings are even more aggressive, moving from a current 4 to 6 ns to less than 2 ns, he added.
The power of 0.25-micron silicon enables such aggressive timings, but submicron parts create other woes. Such chips typically have cores that run at 2.5 to 1.5 V, while PCI requires 5- or 3.3-V signaling, raising the need for voltage-level translators and output buffers that further complicate system timing. "It's doable but the timings get tight," said Questo.
The tighter specs would likely force the industry to use phase-locked loops and spread-spectrum clocks to cut jitter and electromagnetic interference, rather than keep using oscillator clocks.
At press time, the SIG was debating a recommendation to make the PCI-X specs apply to both 64- and 32-bit cards. "You will need controllers that can handle signaling from 33 to 133 MHz. The timings are extremely tight," Questo said. "I have concerns with adding cost and complexity to desktops if they quickly go for [the 32-bit spec]."
More than 40 companies have requested copies of the PCI-X spec, said Bradicich. "The scuttlebutt tells me we will see implementations in late 1999."