Error-correction coding is one of the most powerful tools available to the communications engineer for maximizing data rate reliability, while minimizing transmission energy and system complexity. The higher the performance of the error-correction code, the more flexibility the designer has in determining the required transmission energy, bandwidth and system complexity. A small improvement in error-correction performance can yield large savings in the overall cost of the system.
Error-correction encoding is the addition of redundancy, for example parity-check symbols, to a message that is to be transmitted over a medium-the communication channel. This redundancy allows the error-correction decoder to detect and/or correct erroneous data and restore the received data stream to the original data stream. Error-correction coding has applications wherever digital data is transmitted over an imperfect-noisy-medium such as the Very Small Aperture Terminal (VSAT) satellite communications system, as well as in many other digital-communications and storage systems.
The ability of forward-error-correction code to increase the signal-to-noise capability of a communications channel depends on the code used and the characteristics of the channel. All forward-error-correction codes have a theoretical limit, the Shannon Limit, to their ability to correct a corrupted data stream. The Shannon Limit defines the optimum theoretical boundary for a given code rate. No error-correction code can perform above the Shannon Limit, and as a code approaches this limit, its complexity and code-block size increase exponentially. Another result of the Shannon Limit is that the lower the code rate, the lower the limit on information bit energy/normalized noise.
Error correction schemes are compared to ideal
The code that performs the closest to the Shannon Limit out of all available codes can provide the user with the highest value and improvement to the communication system.
Reed-Solomon (RS) error-correction codes represent one of several standard algorithms for forward error correction that addresses a broad range of applications. They are used as the standard error-correction code for VSAT, Intelsat, digital video broadcast and elsewhere. Reed-Solomon codes concatenated with Viterbi codes offer an improvement over standalone Reed-Solomon codes in terms of bit-error-rate performance. They represent what has been up until now the state of the art for commercially viable forward error correction. The decoding of a block of code can be done with hard- or soft-decision input, and the decoder may output hard- or soft-decision data.
A soft-decision decoder receives not only the binary value of one or zero, but also a confidence value associated with the given bit. If the demodulator is certain that the bit is a one, it places a very high confidence on it. If it is less certain, it places a lower confidence value. A soft in/soft out (SISO) decoder both receives soft-decision data and produces soft-decision output.
The concept of SISO decoders has been applied to the relatively new decoding method called turbo codes. A turbo code feeds demodulated soft-decision data into a SISO decoder. The output of this decoder is then fed into the same or a different SISO decoder. The output of this decoder is then fed back again. This iterative process continues until a confident solution is reached. The concept of feeding the output back into the input is similar to the turbocharger of an engine, and hence the name, "Turbo Codes."
For a turbo code to be effective, the given data must be encoded with two or more different codes. Then, when decoding, each of the codes will modify the confidence of each bit. Each code pushes the confidence of a given bit higher or lower, and consequently changes the hard-decision value of the bits in error. Eventually, the data will settle on an arrangement where all codes are pushing the confidence of all bits higher. The hard-decision values at this point are closer to-hopefully the same as-the transmitted data.
In the market today, the term "turbo code" generally refers to turbo convolutional codes. These codes are built around convolutional codes as opposed to block codes, which are used for turbo product codes. The decoding is done in an iterative fashion, similar to the decoding of the turbo product codes, but with a different SISO decoder.
The complexity of turbo convolutional codes has prevented development of low-cost decoding devices. On the other hand, turbo product codes have been implemented in software by Efficient Channel Coding Inc. and in hardware as a single integrated circuit, the AHA4501 TPC encoder/decoder, by Advanced Hardware Architectures. AHA has developed a single-chip device with performance that parallels what the literature describes as "near-optimal performance."
With turbo product codes, the number of iterations performed per array can be programmed to increase the data rate or increase decoder performance. For higher data-rate applications, only two or three iterations may be performed, still achieving performance superior to Reed-Solomon/Viterbi.
The nature of the algorithm allows the decoder to determine if it has converged upon a valid transmitted block, indicating that further iterations will not modify the data. This feature can be used for channels with varying noise conditions. The decoder can be configured to spend more time decoding blocks with more noise, and spend less time on blocks with little noise, yielding an overall system data-rate improvement.